diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-07-07 09:21:22 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-07-10 16:42:28 +0000 |
| commit | c8062ff9b485f75648003884222ccb6a6d814e93 (patch) | |
| tree | c846fc18062f1b07b0730586268c30708bba749d | |
| parent | 2c06ef9f8c4b96bc2970f812f0beddde374e3c3b (diff) | |
mb/google/rex/var/ovis: Enable both Memory Channels (MC0 and MC1)
This patch skips reading the MEM_CH_SEL GPIO aka GPP_E13 to determine
the memory channel configuration. The signal behavior is not proper,
hence limiting the DIMM capacity to half (only MC0 is enabled).
This patch always reports the full memory capacity as in dual channel
(both MC0 and MC1 enabled).
This change is necessary to ensure that the system reports the correct
memory capacity, even if the MEM_CH_SEL GPIO is not working properly.
BUG=b:290174538
TEST=Able to detect 32GB memory capacity while booting google/ovis.
Without this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 16183080 kB
With this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 32673664 kB
Change-Id: I6c3fa941abb044b79b13785f7b65d09957f0487d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76359
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
| -rw-r--r-- | src/mainboard/google/rex/variants/ovis/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/ovis/memory.c | 16 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/ovis/Makefile.inc b/src/mainboard/google/rex/variants/ovis/Makefile.inc index 2fa692abed..b7851227d7 100644 --- a/src/mainboard/google/rex/variants/ovis/Makefile.inc +++ b/src/mainboard/google/rex/variants/ovis/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/google/rex/variants/ovis/memory.c b/src/mainboard/google/rex/variants/ovis/memory.c new file mode 100644 index 0000000000..f3cdf5ff28 --- /dev/null +++ b/src/mainboard/google/rex/variants/ovis/memory.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-3.0-or-later */ + +#include <baseboard/variants.h> + +bool variant_is_half_populated(void) +{ + /* + * FIXME: b/290253752 - Memory Capacity is incorrect + * MEM_CH_SEL GPIO (GPP_E13) is not working as expected on Ovis as result + * channel select configuration is set to single (MC0) instead dual (MC0/1). + * Only MC0 is reporting DIMM attached and MC1 is disable. + * + * W/A: Always report full memory capacity as in dual channel (MC0/1). + */ + return false; +} |