Leave SSE and MMX instructions enabled in coreboot

In order to use SSE+MMX optimized payloads we don't want to disable SSE+MMX
instructions in the CPU after romstage.

Change-Id: I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/553
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

3 files changed, 0 insertions, 75 deletions

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 54f0f82da5..cbe38dd56d 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -204,13 +204,6 @@ endif
 
 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_disable.inc
-endif
-ifeq ($(CONFIG_MMX),y)
-crt0s += $(src)/cpu/x86/mmx_disable.inc
-endif
-
 ifeq ($(CONFIG_ROMCC),y)
 crt0s += $(src)/arch/x86/init/crt0_romcc_epilogue.inc
 endif
diff --git a/src/cpu/x86/mmx_disable.inc b/src/cpu/x86/mmx_disable.inc
deleted file mode 100644
index 1a4e70f0c6..0000000000
--- a/src/cpu/x86/mmx_disable.inc
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
-
diff --git a/src/cpu/x86/sse_disable.inc b/src/cpu/x86/sse_disable.inc
deleted file mode 100644
index 37458c9cd2..0000000000
--- a/src/cpu/x86/sse_disable.inc
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	/*
-	 * Put the processor back into a reset state
-	 * with respect to the XMM registers.
-	 */
-	xorps %xmm0, %xmm0
-	xorps %xmm1, %xmm1
-	xorps %xmm2, %xmm2
-	xorps %xmm3, %xmm3
-	xorps %xmm4, %xmm4
-	xorps %xmm5, %xmm5
-	xorps %xmm6, %xmm6
-	xorps %xmm7, %xmm7
-
-	/*
-	 * Disable SSE instructions.
-	 *
-	 * Clear CR4[9] (OSFXSR) and CR4[10] (OSXMMEXCPT) so that the
-	 * processor can no longer execute SSE instructions, and unmasked
-	 * SIMD floating point exceptions will generate an invalid opcode
-	 * exception (#UD).
-	 */
-	movl	%cr4, %eax
-	andl	$~(3 << 9), %eax
-	movl	%eax, %cr4
-