diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-01-07 12:17:36 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-19 16:25:22 +0100 |
| commit | c6950576afb4b1e1a2e367b85d9826c16c7504b6 (patch) | |
| tree | e47e400d9a034e4590cde9729e97322212fa52b0 | |
| parent | 3e5c12691f217477cbf30bdbfb651d2d7da9142f (diff) | |
google/lars: Set Correct RCOMP Target for LARs EVT boards
Below are the correct RCOMP Target Values:
Samsung K4E6E304EB part = {100, 40, 40, 21, 40}
The rest of the DIMMs should have RCOMP set to
{100, 40, 40, 23, 40}
LARs EVT has new DIMM configurations, and the earlier RCOMP
settings are not correct for the newly added DIMM cards,
causing reboot issues.
With this patch all the DIMMs get the required values programmed.
BRANCH=None
BUG=None
TEST=Built for Lars EVT SKU1/2/3 and verified Boot to OS.
No Reboot after this change.
Change-Id: I5fa5ce47b4b47198b0ae8d0b57f7729cb57d23bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d29cc8a4ad9bc2b7680e4df146ce281738e4a3c4
Original-Change-Id: I15195b748213553907ff22dbc74651d70f3c7bb6
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320527
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13005
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/mainboard/google/lars/pei_data.c | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/src/mainboard/google/lars/pei_data.c b/src/mainboard/google/lars/pei_data.c index deb488ef4c..67d8644e23 100644 --- a/src/mainboard/google/lars/pei_data.c +++ b/src/mainboard/google/lars/pei_data.c @@ -22,6 +22,7 @@ /* PCH_MEM_CFG[3:0] */ #define MAX_MEMORY_CONFIG 0x10 +#define K4E6E304EB_MEM_ID 0x5 #define RCOMP_TARGET_PARAMS 0x5 void mainboard_fill_pei_data(struct pei_data *pei_data) @@ -41,19 +42,28 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) const u16 RcompResistor[3] = { 200, 81, 162 }; /* Rcomp target */ - static const u16 RcompTarget[MAX_MEMORY_CONFIG][RCOMP_TARGET_PARAMS] = { - { 100, 40, 40, 23, 40 }, - { 100, 40, 40, 23, 40 }, - { 100, 40, 40, 23, 40 }, - /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/ - { 100, 40, 40, 21, 40 }, }; + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 + }; + /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EB -EGCF*/ + static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 21, 40 + }; + + /* Default Rcomp Target assignment */ + const u16 *targeted_rcomp = RcompTarget; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); memcpy(pei_data->RcompResistor, RcompResistor, sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, &RcompTarget[pei_data->mem_cfg_id][0], - sizeof(RcompTarget[pei_data->mem_cfg_id])); + + /* Override Rcomp Target assignment for specific SKU(s) */ + if (pei_data->mem_cfg_id == K4E6E304EB_MEM_ID) + targeted_rcomp = StrengthendRcompTarget; + + memcpy(pei_data->RcompTarget, targeted_rcomp, + sizeof(pei_data->RcompTarget)); } |