diff options
| author | Scott Chao <scott_chao@wistron.corp-partner.google.com> | 2022-04-18 11:20:52 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-27 12:27:38 +0000 |
| commit | c48070798689cc4d4e5c8fd64d43359423023b81 (patch) | |
| tree | 4a831cf6522c5efded0bf0683956220660e36cb4 | |
| parent | ab58d2b488e72334458f774a254dbeffaa63a219 (diff) | |
mb/google/brya/var/crota: enable boot from SSD/ eMMC
- Fix eMMC reset/ enable GPIO pins.
- Fix clk_req and clk_src
BUG=b:229437061
BRANCH=none
TEST=build and boot without error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Id16e292ec7557d1780516a267bd752014d98e463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/crota/overridetree.cb | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index 7a6b99e984..5a48a5edc6 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -84,8 +84,8 @@ chip soc/intel/alderlake end device ref pcie_rp3 on chip soc/intel/common/block/pcie/rtd3 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" register "srcclk_pin" = "1" device generic 0 alias emmc_rtd3 on end end @@ -96,6 +96,7 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end #PCIE3 BH799BB + device ref pcie_rp9 off end device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" @@ -120,10 +121,10 @@ chip soc/intel/alderlake end end #PCIE8 SD card device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 1 + # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ - .clk_req = 1, - .clk_src = 1, + .clk_req = 0, + .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end |