ACPI GNVS: Drop most dev_count_cpu()

Only amd/picasso and amd/stoneyridge have reference to
PCNT and that could be replaced with acpigen.

Remove the PCNT name from GNVS OperationRegion elsewhere.

Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

37 files changed, 20 insertions, 77 deletions

diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c
index 663eecb0b2..d1ab6a040a 100644
--- a/src/soc/intel/alderlake/acpi.c
+++ b/src/soc/intel/alderlake/acpi.c
@@ -285,9 +285,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Enable DPTF based on mainboard configuration */
 	gnvs->dpte = config->dptf_enable;
 
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 63787ede39..773f56eff2 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -80,9 +80,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = ~0ULL;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Enable DPTF based on mainboard configuration */
 	gnvs->dpte = cfg->dptf_enable;
 
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 8b03713f05..97677ad02e 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -12,7 +12,7 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	PCNT,	8,      // 0x00 - Processor Count
+	,	8,      // 0x00 - Processor Count
 	PPCM,	8,      // 0x01 - Max PPC State
 	LIDS,	8,      // 0x02 - LID State
 	PWRS,	8,      // 0x03 - AC Power State
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index ae1ae42e1d..1f2b8ad4f7 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -13,7 +13,7 @@
 
 struct __packed global_nvs {
 	/* Miscellaneous */
-	uint8_t		pcnt; /* 0x00 - Processor Count */
+	uint8_t		unused_was_pcnt; /* 0x00 - Processor Count */
 	uint8_t		ppcm; /* 0x01 - Max PPC State */
 	uint8_t		lids; /* 0x02 - LID State */
 	uint8_t		pwrs; /* 0x03 - AC Power State */
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index cf031b9650..d379bebd81 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -61,9 +61,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Top of Low Memory (start of resource allocation) */
 	gnvs->tolm = nc_read_top_of_low_memory();
 }
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index ad77a832a8..def3fc8f1f 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	P80D,	32,	/* 0x0b - Debug port (IO 0x80) value */
 	LIDS,	 8,	/* 0x0f - LID state (open = 1) */
 	PWRS,	 8,	/* 0x10 - Power State (AC = 1) */
-	PCNT,	 8,	/* 0x11 - Processor count */
+	,	 8,	/* 0x11 - Processor count */
 	TPMP,	 8,	/* 0x12 - TPM Present and Enabled */
 	TLVL,	 8,	/* 0x13 - Throttle Level */
 	PPCM,	 8,	/* 0x14 - Maximum P-state usable by OS */
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 1640886d6c..105d304f66 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -21,7 +21,7 @@ struct __packed global_nvs {
 	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
 	u8	lids; /* 0x0f - LID state (open = 1) */
 	u8	pwrs; /* 0x10 - Power state (AC = 1) */
-	u8	pcnt; /* 0x11 - Processor Count */
+	u8	unused_was_pcnt; /* 0x11 - Processor Count */
 	u8	tpmp; /* 0x12 - TPM Present and Enabled */
 	u8	tlvl; /* 0x13 - Throttle Level */
 	u8	ppcm; /* 0x14 - Maximum P-state usable by OS */
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index b6a361529a..70fd9930d9 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -64,9 +64,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Top of Low Memory (start of resource allocation) */
 	gnvs->tolm = nc_read_top_of_low_memory();
 
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index c983d93db7..564eb43788 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	P80D,	32,	/* 0x0b - Debug port (IO 0x80) value */
 	LIDS,	 8,	/* 0x0f - LID state (open = 1) */
 	PWRS,	 8,	/* 0x10 - Power State (AC = 1) */
-	PCNT,	 8,	/* 0x11 - Processor count */
+	,	 8,	/* 0x11 - Processor count */
 	TPMP,	 8,	/* 0x12 - TPM Present and Enabled */
 	TLVL,	 8,	/* 0x13 - Throttle Level */
 	PPCM,	 8,	/* 0x14 - Maximum P-state usable by OS */
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 2ea114b00c..41bb5a1a54 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -21,7 +21,7 @@ struct __packed global_nvs {
 	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
 	u8	lids; /* 0x0f - LID state (open = 1) */
 	u8	pwrs; /* 0x10 - Power state (AC = 1) */
-	u8      pcnt; /* 0x11 - Processor Count */
+	u8      unused_was_pcnt; /* 0x11 - Processor Count */
 	u8	tpmp; /* 0x12 - TPM Present and Enabled */
 	u8	tlvl; /* 0x13 - Throttle Level */
 	u8	ppcm; /* 0x14 - Maximum P-state usable by OS */
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index e0e805253a..1b6a231651 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -18,7 +18,7 @@ struct __packed global_nvs {
 	u8	lckf; /* 0x08 - Global Lock function for EC */
 	u8	prm4; /* 0x09 - Lock function parameter */
 	u8	prm5; /* 0x0a - Lock function parameter */
-	u8      pcnt; /* 0x0b - Processor Count */
+	u8      unused_was_pcnt; /* 0x0b - Processor Count */
 	u8	ppcm; /* 0x0c - Max PPC State */
 	u8	tmps; /* 0x0d - Temperature Sensor ID */
 	u8	tlvl; /* 0x0e - Throttle Level Limit */
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
index 7ee7e1396e..b83b957c6c 100644
--- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl
@@ -26,7 +26,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LCKF,	8,	// 0x08 - Global Lock function for EC
 	PRM4,	8,	// 0x09 - Lock function parameter
 	PRM5,	8,	// 0x0a - Lock function parameter
-	PCNT,	8,	// 0x0b - Processor Count
+	,	8,	// 0x0b - Processor Count
 	PPCM,	8,	// 0x0c - Max PPC State
 	TMPS,	8,	// 0x0d - Temperature Sensor ID
 	TLVL,	8,	// 0x0e - Throttle Level Limit
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 69f2741465..cf6e7d7177 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -604,9 +604,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 {
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
-
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
 }
 
 static unsigned long broadwell_write_acpi_tables(const struct device *device,
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index b8fa9a7eea..bfb719f1c9 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -189,9 +189,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Enable DPTF based on mainboard configuration */
 	gnvs->dpte = config->dptf_enable;
 
diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index 1333857cb3..6a6970f0a0 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -19,7 +19,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	/* Miscellaneous */
 	OSYS,	16,	// 0x00 - Operating System
 	SMIF,	8,	// 0x02 - SMI function
-	PCNT,	8,	// 0x03 - Processor Count
+	,	8,	// 0x03 - Processor Count
 	PPCM,	8,	// 0x04 - Max PPC State
 	TLVL,	8,	// 0x05 - Throttle Level Limit
 	LIDS,	8,	// 0x06 - LID State
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index 2f3ac1cc0b..abc3400912 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -9,7 +9,7 @@ struct __packed global_nvs {
 	/* Miscellaneous */
 	u16	osys; /* 0x00 - 0x01 Operating System */
 	u8	smif; /* 0x02 - SMI function call ("TRAP") */
-	u8	pcnt; /* 0x03 - Processor Count */
+	u8	unused_was_pcnt; /* 0x03 - Processor Count */
 	u8	ppcm; /* 0x04 - Max PPC State */
 	u8	tlvl; /* 0x05 - Throttle Level Limit */
 	u8	lids; /* 0x06 - LID State */
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index 9618f1f71e..6ab89af401 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -62,9 +62,6 @@ static acpi_cstate_t cstate_map[] = {
 
 void soc_fill_gnvs(struct global_nvs *gnvs)
 {
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Top of Low Memory (start of resource allocation) */
 	gnvs->tolm = (uintptr_t)cbmem_top();
 
diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
index bf880edf62..97fa02f4a2 100644
--- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl
+++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl
@@ -29,7 +29,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	P80D,	32,	// 0x0b - Debug port (IO 0x80) value
 	LIDS,	 8,	// 0x0f - LID state (open = 1)
 	PWRS,	 8,	// 0x10 - Power State (AC = 1)
-	PCNT,	 8,	// 0x11 - Processor count
+	,	 8,	// 0x11 - Processor count
 	TPMP,	 8,	// 0x12 - TPM Present and Enabled
 	TLVL,	 8,	// 0x13 - Throttle Level
 	PPCM,	 8,	// 0x14 - Maximum P-state usable by OS
diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h
index 4aaabc9538..a978d18dc8 100644
--- a/src/soc/intel/denverton_ns/include/soc/nvs.h
+++ b/src/soc/intel/denverton_ns/include/soc/nvs.h
@@ -18,7 +18,7 @@ struct __packed global_nvs {
 	u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
 	u8 lids;  /* 0x0f - LID state (open = 1) */
 	u8 pwrs;  /* 0x10 - Power state (AC = 1) */
-	u8 pcnt;  /* 0x11 - Processor Count */
+	u8 unused_was_pcnt;  /* 0x11 - Processor Count */
 	u8 tpmp;  /* 0x12 - TPM Present and Enabled */
 	u8 tlvl;  /* 0x13 - Throttle Level */
 	u8 ppcm;  /* 0x14 - Maximum P-state usable by OS */
diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c
index 4ea3e25218..88336feae2 100644
--- a/src/soc/intel/elkhartlake/acpi.c
+++ b/src/soc/intel/elkhartlake/acpi.c
@@ -253,9 +253,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Enable DPTF based on mainboard configuration */
 	gnvs->dpte = config->dptf_enable;
 
diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index a9e56facd8..4a84446bc1 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -184,9 +184,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Enable DPTF based on mainboard configuration */
 	gnvs->dpte = config->dptf_enable;
 
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
index e480f55a9e..ea5fb0b303 100644
--- a/src/soc/intel/jasperlake/acpi.c
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -280,9 +280,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Enable DPTF based on mainboard configuration */
 	gnvs->dpte = config->dptf_enable;
 
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index fcee9cd2b7..99a52d15f1 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -163,9 +163,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Enable DPTF based on mainboard configuration */
 	gnvs->dpte = config->dptf_enable;
 
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index 913d2cf610..928c5e6eac 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -27,7 +27,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	LCKF,	8,	// 0x08 - Global Lock function for EC
 	PRM4,	8,	// 0x09 - Lock function parameter
 	PRM5,	8,	// 0x0a - Lock function parameter
-	PCNT,	8,	// 0x0b - Processor Count
+	,	8,	// 0x0b - Processor Count
 	PPCM,	8,	// 0x0c - Max PPC State
 	TMPS,	8,	// 0x0d - Temperature Sensor ID
 	TLVL,	8,	// 0x0e - Throttle Level Limit
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 3d48d4d486..39271d3549 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -17,7 +17,7 @@ struct __packed global_nvs {
 	u8	lckf; /* 0x08 - Global Lock function for EC */
 	u8	prm4; /* 0x09 - Lock function parameter */
 	u8	prm5; /* 0x0a - Lock function parameter */
-	u8      pcnt; /* 0x0b - Processor Count */
+	u8      unused_was_pcnt; /* 0x0b - Processor Count */
 	u8	ppcm; /* 0x0c - Max PPC State */
 	u8	tmps; /* 0x0d - Temperature Sensor ID */
 	u8	tlvl; /* 0x0e - Throttle Level Limit */
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 69b7b1792f..354e3d267d 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -280,9 +280,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
 
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-
 	/* Enable DPTF based on mainboard configuration */
 	gnvs->dpte = config->dptf_enable;
 
diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
index 9d5f47bdaf..99326ee6a4 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi_gnvs.h>
 #include <acpi/acpigen.h>
 #include <arch/smp/mpspec.h>
 #include <assert.h>
@@ -14,7 +13,6 @@
 #include <soc/cpu.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
-#include <soc/nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/soc_util.h>
@@ -28,13 +26,6 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
-void soc_fill_gnvs(struct global_nvs *gnvs)
-{
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-	printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt);
-}
-
 int soc_madt_sci_irq_polarity(int sci)
 {
 	if (sci >= 20)
diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c
index 0575d62a13..2d286231a6 100644
--- a/src/soc/intel/xeon_sp/skx/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi_gnvs.h>
 #include <acpi/acpigen.h>
 #include <arch/smp/mpspec.h>
 #include <assert.h>
@@ -13,7 +12,6 @@
 #include <soc/cpu.h>
 #include <soc/iomap.h>
 #include <soc/msr.h>
-#include <soc/nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/soc_util.h>
@@ -27,13 +25,6 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
-void soc_fill_gnvs(struct global_nvs *gnvs)
-{
-	/* CPU core count */
-	gnvs->pcnt = dev_count_cpu();
-	printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt);
-}
-
 int soc_madt_sci_irq_polarity(int sci)
 {
 	if (sci >= 20)
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index 9194f3f5ce..c6c7397031 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -58,7 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PCP0,	 8,	// 0x2a - PDC CPU/CORE 0
 	PCP1,	 8,	// 0x2b - PDC CPU/CORE 1
 	PPCM,	 8,	// 0x2c - Max. PPC state
-	PCNT,	 8,	// 0x2d - Processor count
+	,	 8,	// 0x2d - Processor count
 	/* Super I/O & CMOS config */
 	Offset (0x32),
 	NATP,	 8,	// 0x32 -
diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
index bbfa4c8d21..25e5b6edac 100644
--- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h
+++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
@@ -49,7 +49,7 @@ struct __packed global_nvs {
 	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
 	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
 	u8	ppcm; /* 0x2c - Max. PPC state */
-	u8      pcnt; /* 0x2d - Processor Count */
+	u8      unused_was_pcnt; /* 0x2d - Processor Count */
 	u8	rsvd4[4];
 	/* Super I/O & CMOS config */
 	u8	natp; /* 0x32 - SIO type */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index c2e7a86f09..a351bc3900 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -645,7 +645,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 {
 	gnvs->apic = 1;
 	gnvs->mpen = 1; /* Enable Multi Processing */
-	gnvs->pcnt = dev_count_cpu();
 }
 
 static const char *lpc_acpi_name(const struct device *dev)
diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
index 62e388801c..314141e65f 100644
--- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
+++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
@@ -58,7 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PCP0,	 8,	// 0x2a - PDC CPU/CORE 0
 	PCP1,	 8,	// 0x2b - PDC CPU/CORE 1
 	PPCM,	 8,	// 0x2c - Max. PPC state
-	PCNT,	 8,	// 0x2d - Processor count
+	,	 8,	// 0x2d - Processor count
 	/* Super I/O & CMOS config */
 	Offset (0x32),
 	NATP,	 8,	// 0x32 -
diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
index 895591506d..42d588fdc6 100644
--- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h
+++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
@@ -50,7 +50,7 @@ struct __packed global_nvs {
 	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
 	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
 	u8	ppcm; /* 0x2c - Max. PPC state */
-	u8      pcnt; /* 0x2d - Processor Count */
+	u8      unused_was_pcnt; /* 0x2d - Processor Count */
 	u8	rsvd4[4];
 	/* Super I/O & CMOS config */
 	u8	natp; /* 0x32 - SIO type */
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 9bc8e6be30..e4d64fd78b 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -545,7 +545,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 {
 	gnvs->apic = 1;
 	gnvs->mpen = 1; /* Enable Multi Processing */
-	gnvs->pcnt = dev_count_cpu();
 }
 
 static const char *lpc_acpi_name(const struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index d95d38af10..249954d857 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -59,7 +59,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	PCP0,	 8,	// 0x2a - PDC CPU/CORE 0
 	PCP1,	 8,	// 0x2b - PDC CPU/CORE 1
 	PPCM,	 8,	// 0x2c - Max. PPC state
-	PCNT,	 8,	// 0x2d - Processor count
+	,	 8,	// 0x2d - Processor count
 	/* Super I/O & CMOS config */
 	Offset (0x32),
 	NATP,	 8,	// 0x32 -
diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
index aa35ea05a5..8027fe4b98 100644
--- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h
+++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
@@ -49,7 +49,7 @@ struct __packed global_nvs {
 	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
 	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
 	u8	ppcm; /* 0x2c - Max. PPC state */
-	u8      pcnt; /* 0x2d - Processor Count */
+	u8      unused_was_pcnt; /* 0x2d - Processor Count */
 	u8	rsvd4[4];
 	/* Super I/O & CMOS config */
 	u8	natp; /* 0x32 - SIO type */
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 4868441aaf..2624aa9150 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -683,7 +683,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 {
 	gnvs->apic = 1;
 	gnvs->mpen = 1; /* Enable Multi Processing */
-	gnvs->pcnt = dev_count_cpu();
 }
 
 static const char *lpc_acpi_name(const struct device *dev)