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authorFurquan Shaikh <furquan@google.com>2020-07-14 18:47:38 -0700
committerAaron Durbin <adurbin@chromium.org>2020-07-16 16:45:48 +0000
commitbf9eb00c11b6940051a6bb5234f28ff567f2e748 (patch)
treea42fd0a370c016e48a72976dc1fd529c183af21e
parent56f949cd0c793e0a43d4339ce6e2e8003f5ce978 (diff)
mb/google/zork: Move variant_pcie_gpio_configure() to bootblock
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe GPIOs can be configured early on in bootblock rather than waiting until romstage. This change moves the call to variant_pcie_gpio_configure() to happen in bootblock and drops romstage.c file. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/zork/bootblock.c2
-rw-r--r--src/mainboard/google/zork/romstage.c11
2 files changed, 2 insertions, 11 deletions
diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c
index 11391efd1e..a7636de702 100644
--- a/src/mainboard/google/zork/bootblock.c
+++ b/src/mainboard/google/zork/bootblock.c
@@ -12,4 +12,6 @@ void bootblock_mainboard_early_init(void)
gpios = variant_early_gpio_table(&num_gpios);
program_gpios(gpios, num_gpios);
}
+
+ variant_pcie_gpio_configure();
}
diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c
deleted file mode 100644
index 39f23cff83..0000000000
--- a/src/mainboard/google/zork/romstage.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <baseboard/variants.h>
-#include <soc/gpio.h>
-#include <soc/romstage.h>
-#include <console/console.h>
-
-void mainboard_romstage_entry_s3(int s3_resume)
-{
- variant_pcie_gpio_configure();
-}