diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-04-20 13:14:16 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-27 12:32:48 +0000 |
| commit | bae4a0b5a1e413a8cf0bdce9be51ca006a02758a (patch) | |
| tree | b5c074b92431355b29fcad8f1ac3483c9f106e4b | |
| parent | c2570dc99800070d987bda05c33113930a506fd6 (diff) | |
soc/intel/alderlake: Implement PMC feature lock
This patch locks PMC features like: debug mode configuration and host
read access to PMC XRAM.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/pmc.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/lockdown.c | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index ca11ae933a..d1e63bc5cf 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -76,6 +76,10 @@ extern struct device_operations pmc_ops; #define PRSTS 0x1810 +#define PM_CFG 0x1818 +#define PM_CFG_DBG_MODE_LOCK (1 << 27) +#define PM_CFG_XRAM_READ_DISABLE (1 << 22) + #define S3_PWRGATE_POL 0x1828 #define S3DC_GATE_SUS (1 << 1) #define S3AC_GATE_SUS (1 << 0) diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index f018dbd28d..4b260da1af 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -27,6 +27,8 @@ static void pmc_lockdown_cfg(int chipset_lockdown) if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); setbits32(pmcbase + SSML, SSML_SSL_EN); + setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | + PM_CFG_XRAM_READ_DISABLE); } } |