diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-16 15:02:17 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:38:33 +0000 |
| commit | ba4dbf8c4ce30da00bc933375d77c4235caccbff (patch) | |
| tree | b6031ba8c1a32cf351fd9575c0e108eedee76826 | |
| parent | 4537332d64a66fac1c1d6b615838c54d33fdefab (diff) | |
soc/amd/stoneyridge/romstage.c: Remove repeated word
Change-Id: I38974b532f41830f49b54444d98e6bd7aa417aba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 96103efd87..49279028b6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -80,7 +80,7 @@ asmlinkage void car_stage_entry(void) * * After setting up DRAM, AGESA also completes the configuration * of the MTRRs, setting regions to WB. Anything written to - * memory between now and and when CAR is dismantled will be + * memory between now and when CAR is dismantled will be * in cache and lost. For now, set the regions UC to ensure * the writes get to DRAM. */ |