mb/*/*/romstage.c: Clean up targets with i82801gx

Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
  values;
* fix some comments about decode ranges.

Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

16 files changed, 252 insertions, 266 deletions

diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 92dfe7402d..79cc35dc6f 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -38,7 +38,7 @@
 static void ich7_enable_lpc(void)
 {
 	/* Enable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 
 	/* I/O Decode Ranges
 	 * X60:       0x0210 == 00000010 00010000
@@ -48,7 +48,7 @@ static void ich7_enable_lpc(void)
 	 *            00 = 378h - 37Fh and 778h - 77Fh
 	 *            10 = 3BCh - 3BEh and 7BCh - 7BEh
 	 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
 
 	/* LPC_EN--LPC I/F Enables Register
 	 * X60:       0x1f0d == 00011111 00001101
@@ -102,7 +102,9 @@ static void ich7_enable_lpc(void)
 	 *            interface. This range is selected in the LPC_COM Decode
 	 *            Range Register (D31:F0:80h, bits 3:2).
 	 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3807);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
+			| CNF1_LPC_EN | MC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
+			| COMA_LPC_EN);
 
 	/* GEN1_DEC, LPC Interface Generic Decode Range 1
 	 * X60:       0x1601 0x007c == 00000000 01111100 00010110 00000001
@@ -126,29 +128,19 @@ static void ich7_enable_lpc(void)
 	 *            1 = Enable the GEN1 I/O range to be forwarded to the LPC
 	 *            I/F
 	 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0681);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x000c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0681);
 
 	/* GEN2_DEC, LPC Interface Generic Decode Range 2
 	 * X60:       0x15e1 0x000c == 00000000 00001100 00010101 11100001
 	 * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001
 	 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x1641);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
-
-	/* GEN3_DEC, LPC Interface Generic Decode Range 3
-	 * X60:       0x1681 0x001c == 00000000 00011100 00010110 10000001
-	 * Macbook21: 0x0000 0x0000
-	 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x0000); /* obsolete, because it writes zeros? */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x0000);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c1641);
 
 	/* GEN4_DEC, LPC Interface Generic Decode Range 4
 	 * X60:       0x0000 0x0000
 	 * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001
 	 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x90, 0x0301);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x92, 0x001c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x001c0301);
 }
 
 static void rcba_config(void)
@@ -163,23 +155,24 @@ static void rcba_config(void)
 	RCBA32(0x3108) = 0x10004321;
 
 	/* PCIe Interrupts */
-	RCBA32(0x310c) = 0x00214321;
+	RCBA32(D28IP) = 0x00214321;
 	/* HD Audio Interrupt */
-	RCBA32(0x3110) = 0x00000001;
+	RCBA32(D27IP) = 0x00000001;
 
 	/* dev irq route register */
-	RCBA16(0x3140) = 0x0232;
-	RCBA16(0x3142) = 0x3246;
-	RCBA16(0x3144) = 0x0235;
-	RCBA16(0x3146) = 0x3201;
-	RCBA16(0x3148) = 0x3216;
+	RCBA16(D31IR) = 0x0232;
+	RCBA16(D30IR) = 0x3246;
+	RCBA16(D29IR) = 0x0235;
+	RCBA16(D28IR) = 0x3201;
+	RCBA16(D27IR) = 0x3216;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Disable unused devices */
-	RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
-	RCBA32(0x3418) |= (1 << 0);	/* Required. */
+	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_INTLAN
+		| FD_ACMOD | FD_ACAUD;
+	RCBA32(FD) |= (1 << 0);	/* Required. */
 
 	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
 
@@ -220,14 +213,14 @@ static void early_ich7_init(void)
 	RCBA32(0x0214) = 0x10030549;
 	RCBA32(0x0218) = 0x00020504;
 	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
+	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
+	RCBA32(GCS) = reg32;
 	reg32 = RCBA32(0x3430);
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 24a5cfde39..e9000a6fa7 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -58,8 +58,8 @@ static void mb_lpc_setup(void)
 	RCBA16(D29IR) = 0x0237;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
-	RCBA8(0x31ff);
+	RCBA8(OIC) = 0x03;
+	RCBA8(OIC);
 
 	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 5);
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 69db496437..e03b5ea847 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -107,30 +107,30 @@ static u8 msr_get_fsb(void)
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
 	// Enable COM1
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140f);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
+			| COMA_LPC_EN);
 	// Enable SuperIO Power Management Events
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
-
-	/* range 0x15e0 - 0x10ef */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x40291);
-
-
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801);
+	/* range 0x290 - 0x297 */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291);
 }
 
 static void rcba_config(void)
 {
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Disable unused devices */
-	RCBA32(0x3418) = 0x003c0061;
+	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
+		| FD_ACAUD | 1;
 
 	/* Enable PCIe Root Port Clock Gate */
-	RCBA32(0x341c) = 0x00000001;
+	RCBA32(CG) = 0x00000001;
 }
 
 static void early_ich7_init(void)
@@ -165,14 +165,14 @@ static void early_ich7_init(void)
 	RCBA32(0x0214) = 0x10030509;
 	RCBA32(0x0218) = 0x00020504;
 	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
+	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
+	RCBA32(GCS) = reg32;
 	reg32 = RCBA32(0x3430);
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index ba07e45e99..5ea41ea194 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -78,7 +78,7 @@ static void ich7_enable_lpc(void)
 		COMB_LPC_EN | COMA_LPC_EN);
 
 	/* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */
-	pci_write_config32(LPC_DEV, 0x84, 0x003c0a01);
+	pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01);
 }
 
 void mainboard_romstage_entry(unsigned long bist)
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index d1552a6599..e58ef1bda6 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -57,21 +57,23 @@ static void setup_special_ich7_gpios(void)
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
-	if (read_option(lpt, 0) != 0) {
-	       lpt_en = 1 << 2; // enable LPT
-	}
+	if (read_option(lpt, 0) != 0)
+		lpt_en = LPT_LPC_EN;
+
 	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+			| MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
+			| FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN);
 	// Enable 0x02e0 - 0x2ff
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1);
 	// Enable 0x600 - 0x6ff
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601);
 	// Enable 0x68 - 0x6f
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069);
 }
 
 /* This box has two superios, so enabling serial becomes slightly excessive.
@@ -150,23 +152,23 @@ static void rcba_config(void)
 	//RCBA32(0x001c) = 0x03128010;
 
 	/* Device 1f interrupt pin register */
-	RCBA32(0x3100) = 0x00042220;
+	RCBA32(D31IP) = 0x00042220;
 	/* Device 1d interrupt pin register */
-	RCBA32(0x310c) = 0x00214321;
+	RCBA32(D28IP) = 0x00214321;
 
 	/* dev irq route register */
-	RCBA16(0x3140) = 0x0232;
-	RCBA16(0x3142) = 0x3246;
-	RCBA16(0x3144) = 0x0237;
-	RCBA16(0x3146) = 0x3201;
-	RCBA16(0x3148) = 0x3216;
+	RCBA16(D31IR) = 0x0232;
+	RCBA16(D30IR) = 0x3246;
+	RCBA16(D29IR) = 0x0237;
+	RCBA16(D28IR) = 0x3201;
+	RCBA16(D27IR) = 0x3216;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Disable unused devices */
-	RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
-	RCBA32(0x3418) |= (1 << 0); // Required.
+	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD | FD_PATA;
+	RCBA32(FD) |= (1 << 0); // Required.
 
 	/* Enable PCIe Root Port Clock Gate */
 	// RCBA32(0x341c) = 0x00000001;
@@ -221,7 +223,7 @@ static void early_ich7_init(void)
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 9789d2acf6..926a5a7f36 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -68,27 +68,29 @@ static void setup_sio(void)
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000);
 	// Enable COM1
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
+			| CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMA_LPC_EN);
 	// Enable SuperIO Power Management Events
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801);
 	/* LPC decode range 2: Environment Controller */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040291);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291);
 }
 
 static void rcba_config(void)
 {
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Disable unused devices */
-	RCBA32(0x3418) = 0x003c0061;
+	RCBA32(FD) = 0x003c0061;
 
 	/* Enable PCIe Root Port Clock Gate */
-	RCBA32(0x341c) = 0x00000001;
+	RCBA32(CG) = 0x00000001;
 }
 
 static void early_ich7_init(void)
@@ -123,14 +125,14 @@ static void early_ich7_init(void)
 	RCBA32(0x0214) = 0x10030509;
 	RCBA32(0x0218) = 0x00020504;
 	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
+	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
+	RCBA32(GCS) = reg32;
 	reg32 = RCBA32(0x3430);
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index e71e00cf52..ac336e45f7 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -89,23 +89,23 @@ static void mb_gpio_init(void)
 	ite_reg_write(EC_DEV, 0x30, 0x01); // Enable
 
 	/* IRQ routing */
-	RCBA32(0x3100) = 0x00002210;
-	RCBA32(0x3104) = 0x00002100;
-	RCBA32(0x3108) = 0x10004321;
-	RCBA32(0x310c) = 0x00214321;
-	RCBA32(0x3110) = 0x00000001;
-	RCBA32(0x3140) = 0x00410032;
-	RCBA32(0x3144) = 0x32100237;
-	RCBA32(0x3148) = 0x00000000;
+	RCBA32(D31IP) = 0x00002210;
+	RCBA32(D30IP) = 0x00002100;
+	RCBA32(D29IP) = 0x10004321;
+	RCBA32(D28IP) = 0x00214321;
+	RCBA32(D27IP) = 0x00000001;
+	RCBA32(D31IR) = 0x00410032;
+	RCBA32(D29IR) = 0x32100237;
+	RCBA32(D27IR) = 0x00000000;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
-	RCBA8(0x31ff);
+	RCBA8(OIC) = 0x03;
+	RCBA8(OIC);
 
-	RCBA32(0x3410) = 0x00190464;
+	RCBA32(GCS) = 0x00190464;
 	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
 		| FD_ACAUD | 1;
-	RCBA32(0x341c) = 0x00000000;
+	RCBA32(CG) = 0x00000000;
 	RCBA32(0x3430) = 0x00000001;
 	RCBA32(0x3e00) = 0xff000001;
 	RCBA32(0x3e08) = 0x00000080;
@@ -119,15 +119,14 @@ static void mb_gpio_init(void)
 static void ich7_enable_lpc(void)
 {
 	/* Disable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
 	/* Decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
 		CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN
 			| LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
 
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291);
 }
 
 void mainboard_romstage_entry(unsigned long bist)
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 43c56778ba..0d3b839b8e 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -42,15 +42,17 @@
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
 	// Enable COM1/COM2/KBD/SuperIO1+2
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
+			| CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN
+			| COMB_LPC_EN);
 	// Enable HWM at 0x290
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291);
 	// io 0x300 decode
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);
 }
 
 /* This box has one superio
@@ -131,19 +133,19 @@ static void rcba_config(void)
 	//RCBA32(0x001c) = 0x03128010;
 
 	/* Device 1f interrupt pin register */
-	RCBA32(0x3100) = 0x00042210;
+	RCBA32(D31IP) = 0x00042210;
 	/* Device 1d interrupt pin register */
-	RCBA32(0x310c) = 0x00214321;
+	RCBA32(D28IP) = 0x00214321;
 
 	/* dev irq route register */
-	RCBA16(0x3140) = 0x0132;
-	RCBA16(0x3142) = 0x0146;
-	RCBA16(0x3144) = 0x0237;
-	RCBA16(0x3146) = 0x3201;
-	RCBA16(0x3148) = 0x0146;
+	RCBA16(D31IR) = 0x0132;
+	RCBA16(D30IR) = 0x0146;
+	RCBA16(D29IR) = 0x0237;
+	RCBA16(D28IR) = 0x3201;
+	RCBA16(D27IR) = 0x0146;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Enable PCIe Root Port Clock Gate */
 	// RCBA32(0x341c) = 0x00000001;
@@ -181,14 +183,14 @@ static void early_ich7_init(void)
 	RCBA32(0x0214) = 0x10030549;
 	RCBA32(0x0218) = 0x00020504;
 	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
+	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
+	RCBA32(GCS) = reg32;
 	reg32 = RCBA32(0x3430);
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index c6406e6f9f..b2044c1a30 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -57,15 +57,15 @@ static void mb_gpio_init(void)
 static void nm10_enable_lpc(void)
 {
 	/* Disable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00);
 	/* Decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80,
-		pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x80) | 0x0010);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
-		CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC,
+		pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
+			| CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN
+			| COMB_LPC_EN);
 
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291);
 }
 
 static void rcba_config(void)
@@ -74,29 +74,19 @@ static void rcba_config(void)
 	RCBA32(0x0014) = 0x80000001;
 	RCBA32(0x001c) = 0x03128010;
 
-	/* Device 1f interrupt pin register */
-	RCBA32(0x3100) = 0x00042210;
-	RCBA32(0x3108) = 0x10004321;
-
-	RCBA32(0x3104) = 0x00002100;
-
-	/* PCIe Interrupts */
-	RCBA32(0x310c) = 0x00214321;
-	/* HD Audio Interrupt */
-	RCBA32(0x3110) = 0x00000001;
-
 	/* dev irq route register */
-	RCBA16(0x3140) = 0x0132;
-	RCBA16(0x3142) = 0x0146;
-	RCBA16(0x3144) = 0x0237;
-	RCBA16(0x3146) = 0x3201;
-	RCBA16(0x3148) = 0x0146;
+	RCBA16(D31IR) = 0x0132;
+	RCBA16(D30IR) = 0x0146;
+	RCBA16(D29IR) = 0x0237;
+	RCBA16(D28IR) = 0x3201;
+	RCBA16(D27IR) = 0x0146;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
-	RCBA32(0x3418) = 0x003000e2;
-	RCBA32(0x3418) |= 1;
+	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD
+		| FD_PATA;
+	RCBA32(FD) |= 1;
 }
 
 void mainboard_romstage_entry(unsigned long bist)
@@ -113,7 +103,7 @@ void mainboard_romstage_entry(unsigned long bist)
 		enable_lapic();
 
 	/* Disable watchdog timer */
-	RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
+	RCBA32(GCS) = RCBA32(GCS) | 0x20;
 
 	/* Set southbridge and Super I/O GPIOs. */
 	mb_gpio_init();
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index e769fc522b..27c1e3e7db 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -40,13 +40,14 @@
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// Set COM1/COM2 decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
 	// Enable COM1
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
+			| FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
 	// Enable SuperIO Power Management Events
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681);
 }
 
 static void rcba_config(void)
@@ -55,26 +56,21 @@ static void rcba_config(void)
 	//RCBA32(0x0014) = 0x80000001;
 	//RCBA32(0x001c) = 0x03128010;
 
-	/* Device 1f interrupt pin register */
-	RCBA32(0x3100) = 0x00042210;
-	/* Device 1d interrupt pin register */
-	RCBA32(0x310c) = 0x00214321;
-
 	/* dev irq route register */
-	RCBA16(0x3140) = 0x0132;
-	RCBA16(0x3142) = 0x0146;
-	RCBA16(0x3144) = 0x0237;
-	RCBA16(0x3146) = 0x3201;
-	RCBA16(0x3148) = 0x0146;
+	RCBA16(D31IR) = 0x0132;
+	RCBA16(D30IR) = 0x0146;
+	RCBA16(D29IR) = 0x0237;
+	RCBA16(D28IR) = 0x3201;
+	RCBA16(D27IR) = 0x0146;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Disable unused devices */
-	//RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
-	// RCBA32(0x3418) |= (1 << 0); // Required.
-	// FIXME look me up!
-	RCBA32(0x3418) = 0x003204e1;
+	// FIXME devicetree disables pcie3 not 2.
+	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE2 | (1 << 10) | FD_INTLAN
+		| FD_ACMOD | FD_ACAUD;
+	RCBA32(FD) |= 1;
 
 	/* Enable PCIe Root Port Clock Gate */
 	// RCBA32(0x341c) = 0x00000001;
@@ -119,7 +115,7 @@ static void early_ich7_init(void)
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 3b3ff661fd..f7e8131a5e 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -41,23 +41,25 @@
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
-	if (read_option(lpt, 0) != 0) {
-		lpt_en = 1 << 2; /* enable LPT */
-	}
+	if (read_option(lpt, 0) != 0)
+		lpt_en = LPT_LPC_EN; /* enable LPT */
+
 	/* Enable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	/* Set COM1/COM2 decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
 	/* Enable COM1/COM2/KBD/SuperIO1+2 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,  CNF2_LPC_EN
+			| CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN
+			| COMB_LPC_EN | lpt_en);
 	/* Enable HWM at 0xa00 */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);
 	/* COM3 decode */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9);
 	/* COM4 decode */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9);
 	/* io 0x300 decode */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);
 }
 
 /* TODO: superio code should really not be in mainboard */
@@ -186,19 +188,19 @@ static void rcba_config(void)
 	/* Set up virtual channel 0 */
 
 	/* Device 1f interrupt pin register */
-	RCBA32(0x3100) = 0x00042210;
+	RCBA32(D31IP) = 0x00042210;
 	/* Device 1d interrupt pin register */
-	RCBA32(0x310c) = 0x00214321;
+	RCBA32(D28IP) = 0x00214321;
 
 	/* dev irq route register */
-	RCBA16(0x3140) = 0x0132;
-	RCBA16(0x3142) = 0x3241;
-	RCBA16(0x3144) = 0x0237;
-	RCBA16(0x3146) = 0x3210;
-	RCBA16(0x3148) = 0x3210;
+	RCBA16(D31IR) = 0x0132;
+	RCBA16(D30IR) = 0x3241;
+	RCBA16(D29IR) = 0x0237;
+	RCBA16(D28IR) = 0x3210;
+	RCBA16(D27IR) = 0x3210;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Now, this is a bit ugly. As per PCI specification, function 0 of a
 	 * device always has to be implemented. So disabling ethernet port 1
@@ -245,7 +247,7 @@ static void rcba_config(void)
 
 	reg32 |= 1;
 
-	RCBA32(0x3418) = reg32;
+	RCBA32(FD) = reg32;
 
 	/* Enable PCIe Root Port Clock Gate */
 
@@ -283,14 +285,14 @@ static void early_ich7_init(void)
 	RCBA32(0x0214) = 0x10030549;
 	RCBA32(0x0218) = 0x00020504;
 	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
+	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
+	RCBA32(GCS) = reg32;
 	reg32 = RCBA32(0x3430);
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 80b989fc50..18470ea3f8 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -41,23 +41,22 @@
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN
+			| LPT_LPC_EN | COMA_LPC_EN);
 
 	/* range 0x1600 - 0x167f */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601);
 
-	/* range 0x15e0 - 0x10ef */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
+	/* range 0x15e0 - 0x15ef */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1);
 
 	/* range 0x1680 - 0x169f */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681);
 }
 
 static void early_superio_config(void)
@@ -83,27 +82,27 @@ static void rcba_config(void)
 	RCBA32(0x001c) = 0x03128010;
 
 	/* Device 1f interrupt pin register */
-	RCBA32(0x3100) = 0x00001230;
-	RCBA32(0x3108) = 0x40004321;
+	RCBA32(D31IP) = 0x00001230;
+	RCBA32(D29IP) = 0x40004321;
 
 	/* PCIe Interrupts */
-	RCBA32(0x310c) = 0x00004321;
+	RCBA32(D28IP) = 0x00004321;
 	/* HD Audio Interrupt */
-	RCBA32(0x3110) = 0x00000002;
+	RCBA32(D27IP) = 0x00000002;
 
 	/* dev irq route register */
-	RCBA16(0x3140) = 0x1007;
-	RCBA16(0x3142) = 0x0076;
-	RCBA16(0x3144) = 0x3210;
-	RCBA16(0x3146) = 0x7654;
-	RCBA16(0x3148) = 0x0010;
+	RCBA16(D31IR) = 0x1007;
+	RCBA16(D30IR) = 0x0076;
+	RCBA16(D29IR) = 0x3210;
+	RCBA16(D28IR) = 0x7654;
+	RCBA16(D27IR) = 0x0010;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Disable unused devices */
-	RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
-	RCBA32(0x3418) |= (1 << 0); // Required.
+	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
+	RCBA32(FD) |= (1 << 0); // Required.
 
 	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
 	RCBA32(0x1e84) = 0x00020001;
@@ -146,14 +145,14 @@ static void early_ich7_init(void)
 	RCBA32(0x0214) = 0x10030549;
 	RCBA32(0x0218) = 0x00020504;
 	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
+	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
+	RCBA32(GCS) = reg32;
 	reg32 = RCBA32(0x3430);
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index eddb1506bb..0eac15a4ff 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -41,23 +41,21 @@
 static void ich7_enable_lpc(void)
 {
 	// Enable Serial IRQ
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
-
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN
+			| LPT_LPC_EN | COMA_LPC_EN);
 	/* range 0x1600 - 0x167f */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601);
 
-	/* range 0x15e0 - 0x10ef */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
+	/* range 0x15e0 - 0x15ef */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1);
 
 	/* range 0x1680 - 0x169f */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681);
 }
 
 static void early_superio_config(void)
@@ -83,27 +81,27 @@ static void rcba_config(void)
 	RCBA32(0x001c) = 0x03128010;
 
 	/* Device 1f interrupt pin register */
-	RCBA32(0x3100) = 0x00001230;
-	RCBA32(0x3108) = 0x40004321;
+	RCBA32(D31IP) = 0x00001230;
+	RCBA32(D29IP) = 0x40004321;
 
 	/* PCIe Interrupts */
-	RCBA32(0x310c) = 0x00004321;
+	RCBA32(D28IP) = 0x00004321;
 	/* HD Audio Interrupt */
-	RCBA32(0x3110) = 0x00000002;
+	RCBA32(D27IP) = 0x00000002;
 
 	/* dev irq route register */
-	RCBA16(0x3140) = 0x1007;
-	RCBA16(0x3142) = 0x0076;
-	RCBA16(0x3144) = 0x3210;
-	RCBA16(0x3146) = 0x7654;
-	RCBA16(0x3148) = 0x0010;
+	RCBA16(D31IR) = 0x1007;
+	RCBA16(D30IR) = 0x0076;
+	RCBA16(D29IR) = 0x3210;
+	RCBA16(D28IR) = 0x7654;
+	RCBA16(D27IR) = 0x0010;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Disable unused devices */
-	RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
-	RCBA32(0x3418) |= (1 << 0);	// Required.
+	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
+	RCBA32(FD) |= (1 << 0);	// Required.
 
 	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
 	RCBA32(0x1e84) = 0x00020001;
@@ -146,14 +144,14 @@ static void early_ich7_init(void)
 	RCBA32(0x0214) = 0x10030549;
 	RCBA32(0x0218) = 0x00020504;
 	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
+	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
+	RCBA32(GCS) = reg32;
 	reg32 = RCBA32(0x3430);
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index 0b04f863fc..ffb72e3af1 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -45,19 +45,18 @@ static void ich7_enable_lpc(void)
 	// decode range
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
 	// decode range
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, 0x1f0d);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN
+			| MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
+			| FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
 
 	/* range 0x1600 - 0x167f */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601);
 
-	/* range 0x15e0 - 0x10ef */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
+	/* range 0x15e0 - 0x15ef */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1);
 
 	/* range 0x1680 - 0x169f */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681);
 }
 
 static void early_superio_config(void)
@@ -146,7 +145,7 @@ static void early_ich7_init(void)
 	RCBA32(0x0214) = 0x10030549;
 	RCBA32(0x0218) = 0x00020504;
 	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
+	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 6);
 	RCBA32(GCS) = reg32;
 	reg32 = RCBA32(0x3430);
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index a488488b1a..b4611f5bcc 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -39,22 +39,23 @@
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
-	if (read_option(lpt, 0) != 0) {
-	       lpt_en = 1 << 2; /* enable LPT */
-	}
+	if (read_option(lpt, 0) != 0)
+		lpt_en = LPT_LPC_EN; /* enable LPT */
+
 	/* Enable Serial IRQ */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
 	/* decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
 	/* decode range */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en);
-	/* Enable 0x02e0 */
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c);
-	/* COM3 decode */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601);
-	/* COM4 decode */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
+			| MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN
+			| FDD_LPC_EN | lpt_en | COMB_LPC_EN | COMA_LPC_EN);
+	/* COM3 and COM4 decode? */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x1c02e1);
+	/* ??decode?? */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601);
+	/* EC decode? */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069);
 }
 
 /* This box has two superios, so enabling serial becomes slightly excessive.
@@ -121,24 +122,22 @@ static void rcba_config(void)
 	/* Set up virtual channel 0 */
 
 	/* Device 1f interrupt pin register */
-	RCBA32(0x3100) = 0x00042220;
-	/* Device 1d interrupt pin register */
-	RCBA32(0x310c) = 0x00214321;
+	RCBA32(D31IP) = 0x00042220;
 
 	/* dev irq route register */
-	RCBA16(0x3140) = 0x0232;
-	RCBA16(0x3142) = 0x3246;
-	RCBA16(0x3144) = 0x0237;
-	RCBA16(0x3146) = 0x3201;
-	RCBA16(0x3148) = 0x3216;
+	RCBA16(D31IR) = 0x0232;
+	RCBA16(D30IR) = 0x3246;
+	RCBA16(D29IR) = 0x0237;
+	RCBA16(D28IR) = 0x3201;
+	RCBA16(D27IR) = 0x3216;
 
 	/* Enable IOAPIC */
-	RCBA8(0x31ff) = 0x03;
+	RCBA8(OIC) = 0x03;
 
 	/* Disable unused devices */
-	RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
+	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE3 | FD_PCIE2 |
 			 FD_INTLAN | FD_ACMOD | FD_HDAUD | FD_PATA;
-	RCBA32(0x3418) |= (1 << 0); /* Required. */
+	RCBA32(FD) |= (1 << 0); /* Required. */
 
 	/* This should probably go into the ACPI OS Init trap */
 
@@ -183,14 +182,14 @@ static void early_ich7_init(void)
 	RCBA32(0x0214) = 0x10030549;
 	RCBA32(0x0218) = 0x00020504;
 	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
+	reg32 = RCBA32(GCS);
 	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
+	RCBA32(GCS) = reg32;
 	reg32 = RCBA32(0x3430);
 	reg32 &= ~(3 << 0);
 	reg32 |= (1 << 0);
 	RCBA32(0x3430) = reg32;
-	RCBA32(0x3418) |= (1 << 0);
+	RCBA32(FD) |= (1 << 0);
 	RCBA16(0x0200) = 0x2008;
 	RCBA8(0x2027) = 0x0d;
 	RCBA16(0x3e08) |= (1 << 7);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index b3c1b48ec2..df744fc73c 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -125,6 +125,11 @@ int southbridge_detect_s3_resume(void);
 #define   COMB_LPC_EN		(1 << 1)  /* LPC_IO_DEC[6:4] */
 #define   COMA_LPC_EN		(1 << 0)  /* LPC_IO_DEC[2:0] */
 
+#define GEN1_DEC		0x84
+#define GEN2_DEC		0x88
+#define GEN3_DEC		0x8c
+#define GEN4_DEC		0x90
+
 /* PCI Configuration Space (D31:F1): IDE */
 #define INTR_LN			0x3c
 #define IDE_TIM_PRI		0x40	/* IDE timings, primary */