soc/amd/picasso/makefile: order source files alphabetically

Change-Id: I6eb0881ab05730b094caef2a9258c4d4d827195b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

1 files changed, 15 insertions, 15 deletions

diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index e111186e59..d873079b2c 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -15,40 +15,40 @@ all-y += aoac.c
 
 bootblock-y += bootblock.c
 bootblock-y += early_fch.c
-bootblock-y += i2c.c
-bootblock-y += uart.c
 bootblock-y += gpio.c
+bootblock-y += i2c.c
 bootblock-y += reset.c
+bootblock-y += uart.c
 
 romstage-y += fsp_m_params.c
-romstage-y += i2c.c
-romstage-y += romstage.c
 romstage-y += gpio.c
+romstage-y += i2c.c
 romstage-y += reset.c
+romstage-y += romstage.c
 romstage-y += uart.c
 
 verstage-y += i2c.c
 verstage_x86-y += gpio.c
-verstage_x86-y += uart.c
 verstage_x86-y += reset.c
+verstage_x86-y += uart.c
 
-ramstage-y += i2c.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += data_fabric.c
-ramstage-y += root_complex.c
-ramstage-y += mca.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c
-ramstage-y += gpio.c
 ramstage-y += fch.c
-ramstage-y += reset.c
-ramstage-y += sata.c
-ramstage-y += uart.c
-ramstage-y += soc_util.c
 ramstage-y += fsp_s_params.c
+ramstage-y += gpio.c
 ramstage-y += graphics.c
+ramstage-y += i2c.c
+ramstage-y += mca.c
 ramstage-y += pcie_gpp.c
+ramstage-y += reset.c
+ramstage-y += root_complex.c
+ramstage-y += sata.c
+ramstage-y += soc_util.c
+ramstage-y += uart.c
 ramstage-y += xhci.c
 
 smm-y += smihandler.c