diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2021-01-26 20:09:34 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-01-28 20:44:27 +0000 |
| commit | ad4f6d7c6e10027d420d3bae722b734674643873 (patch) | |
| tree | c019d327f3932e3dc30881e3ed9080c39799a31b | |
| parent | 15e379aaf334e7931710b4208ccedf2f9ee44b0d (diff) | |
soc/amd/picasso: allow USB_PD port setting override
Allow to override the RFMUX setting if the board does not use PD chip.
BUG=b:177389383
BRANCH=none
TEST=Build; Check the USB_PD port been override.
Change-Id: Idd559b67668846805005a6e00f5a84655310f348
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49932
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 21 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fch.c | 18 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/i2c.h | 7 |
3 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index be30efa87c..244d7831ec 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -48,7 +48,25 @@ union __packed usb3_force_gen1 { uint8_t usb3_port_force_gen1_en; }; +enum rfmux_configuration_setting { + USB_PD_RFMUX_SAFE_STATE = 0x0, + USB_PD_RFMUX_USB31_MODE = 0x1, + USB_PD_RFMUX_USB31_MODE_FLIP = 0x2, + USB_PD_RFMUX_ATE_MODE = 0x3, + USB_PD_RFMUX_DP_X2_MODE = 0x4, + USB_PD_RFMUX_MF_MODE_ALT_D_F = 0x6, + USB_PD_RFMUX_DP_X2_MODE_FLIP = 0x8, + USB_PD_RFMUX_MF_MODE_ALT_D_F_FLIP = 0x9, + USB_PD_RFMUX_DP_X4_MODE = 0xc, +}; + +struct usb_pd_control { + uint8_t rfmux_override_en; + uint32_t rfmux_config; +}; + #define USB_PORT_COUNT 6 +#define USB_PD_PORT_COUNT 2 enum sd_emmc_driver_strength { SD_EMMC_DRIVE_STRENGTH_B, @@ -257,6 +275,9 @@ struct soc_amd_picasso_config { uint8_t pwron_varybl_to_blon; uint8_t pwrdown_bloff_to_varybloff; uint8_t min_allowed_bl_level; + + /* allow USB PD port setting override */ + struct usb_pd_control usb_pd_config_override[USB_PD_PORT_COUNT]; }; #endif /* __PICASSO_CHIP_H__ */ diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 4fdaa391e7..4db7a8c615 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -101,6 +101,22 @@ void sb_clk_output_48Mhz(void) misc_write32(MISC_CLK_CNTL1, ctrl); } +static void sb_rfmux_config_override(void) +{ + u8 port; + const struct soc_amd_picasso_config *cfg; + + cfg = config_of_soc(); + + for (port = 0; port < USB_PD_PORT_COUNT; port++) { + if (cfg->usb_pd_config_override[port].rfmux_override_en) { + write32((void *)(USB_PD_PORT_CONTROL + PD_PORT_MUX_OFFSET(port)), + cfg->usb_pd_config_override[port].rfmux_config + | USB_PD_RFMUX_OVERRIDE); + } + } +} + static void sb_init_acpi_ports(void) { u32 reg; @@ -218,6 +234,8 @@ void southbridge_init(void *chip_info) gpp_clk_setup(); sb_clk_output_48Mhz(); + + sb_rfmux_config_override(); } void southbridge_final(void *chip_info) diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 3e94a1ad62..41b930b186 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -21,6 +21,13 @@ struct soc_amd_i2c_save { #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx +#define I2C4_USB_PD_CTRL_OFFSET 0x600 +#define USB_PD_PORT_CONTROL (APU_I2C4_BASE + I2C4_USB_PD_CTRL_OFFSET) +#define PD_PORT_MUX_OFFSET(x) (0x10 * (x)) +#define DP_REVERSE BIT(4) +#define USB_PD_RFMUX_OVERRIDE BIT(8) +#define USB_PD_DP_OVERRIDE BIT(9) + void sb_reset_i2c_slaves(void); /* Sets the base address for the specific I2C bus. */ |