diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-07-16 09:52:39 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-07-17 22:03:02 +0000 |
| commit | ab304bc091b793b52cd5a8d1255e6e144727451a (patch) | |
| tree | 651d548ee44469b413288f0042a927d6c321fb57 | |
| parent | 4c15211a782936485203e858da7bf8cea92fce08 (diff) | |
sb/amd/common: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I04951bf142fc4061960f42ad7ae702a70215e658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/southbridge/amd/common/amd_pci_util.c | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/common/amd_pci_util.h | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index cbba3ef096..b9e8a5f930 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -39,11 +39,11 @@ void write_pci_int_idx(u8 index, int mode, u8 data) * given in global variables intr_data and picr_data. * These variables are defined in mainboard.c */ -void write_pci_int_table (void) +void write_pci_int_table(void) { u8 byte; - if (picr_data_ptr == NULL || intr_data_ptr == NULL){ + if (picr_data_ptr == NULL || intr_data_ptr == NULL) { printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n" "'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n"); return; @@ -54,7 +54,7 @@ void write_pci_int_table (void) "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { if (intr_types[byte]) { - write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]); + write_pci_int_idx(byte, 0, (u8)picr_data_ptr[byte]); printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", byte, intr_types[byte], read_pci_int_idx(byte, 0)); } @@ -65,7 +65,7 @@ void write_pci_int_table (void) "\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n"); for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) { if (intr_types[byte]) { - write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]); + write_pci_int_idx(byte, 1, (u8)intr_data_ptr[byte]); printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n", byte, intr_types[byte], read_pci_int_idx(byte, 1)); } diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h index bfcd57a342..15e0fb8f8c 100644 --- a/src/southbridge/amd/common/amd_pci_util.h +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -23,6 +23,6 @@ extern const u8 *picr_data_ptr; u8 read_pci_int_idx(u8 index, int mode); void write_pci_int_idx(u8 index, int mode, u8 data); void write_pci_cfg_irqs(void); -void write_pci_int_table (void); +void write_pci_int_table(void); #endif /* AMD_PCI_UTIL_H */ |