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authorAlan Huang <alan-huang@quanta.corp-partner.google.com>2021-11-10 13:16:53 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-12-03 15:49:44 +0000
commita7ebca39692f44344000c42eee724d359ebc31cf (patch)
treef767f3a013752b056d709727c663c9a4940abedb
parent769994cbf6cf1f136e00f8371c704a38c2e27e63 (diff)
mb/google/brya/var/brask: Enable LAN driver to program MAC
Turn on the LAN device in devicetree and add Kconfig item RT8168_GET_MAC_FROM_VPD to support programming MAC address. BUG=b:193750191 BRANCH=None TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD. Use 'ifconfig' to check if the MAC written successfully. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/mainboard/google/brya/Kconfig1
-rw-r--r--src/mainboard/google/brya/variants/brask/overridetree.cb5
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 6bf1fe122c..b14178ce56 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
def_bool n
select SPD_CACHE_IN_FMAP
select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
+ select RT8168_GET_MAC_FROM_VPD
if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index 2122acdc34..258898dfd3 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -79,6 +79,11 @@ chip soc/intel/alderlake
device generic 0 alias dptf_policy on end
end
end
+ device ref pcie_rp7 on
+ chip drivers/net
+ device pci 00.0 on end
+ end
+ end # RTL8125 Ethernet NIC
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 0
register "cpu_pcie_rp[CPU_RP(1)]" = "{