nb/intel/gm45: Enable 64bit support

This patch does the following:
- Allow selecting 64bit from Kconfig
- Fix up integer to pointer conversion that gcc complains about
- Add a buildtest target in configs

Tested on Thinkpad X200: boots fine to the payload

Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

6 files changed, 15 insertions, 13 deletions

diff --git a/configs/config.lenovo_t400_vboot_and_debug b/configs/config.lenovo_t400_vboot_and_debug
index 2923f94758..39c17e6aca 100644
--- a/configs/config.lenovo_t400_vboot_and_debug
+++ b/configs/config.lenovo_t400_vboot_and_debug
@@ -12,3 +12,4 @@ CONFIG_DEBUG_BOOT_STATE=y
 CONFIG_DEBUG_ADA_CODE=y
 CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y
 CONFIG_VBOOT=y
+CONFIG_USE_EXP_X86_64_SUPPORT=y
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 3f632a1a6f..c186f01737 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -12,6 +12,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS
 	select INTEL_EDID
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_SSC_ALTERNATE_REF
+	select HAVE_EXP_X86_64_SUPPORT
 
 config VBOOT
 	select VBOOT_STARTS_IN_BOOTBLOCK
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index b533de9198..02785bcdd0 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -92,7 +92,7 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* cbmem_top can be shifted downwards due to alignment.
 	   Mark the region between cbmem_top and tomk as unusable */
-	delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10);
+	delta_cbmem = tomk - ((uintptr_t)cbmem_top() >> 10);
 	tomk -= delta_cbmem;
 	uma_sizek += delta_cbmem;
 
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 35d71c009f..4196edf440 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1577,15 +1577,15 @@ static void jedec_init(const timings_t *const timings,
 		const u32 rankaddr = raminit_get_rank_addr(ch, r);
 		printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr);
 		mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(2));
-		read32((u32 *)(rankaddr | WL));
+		read32p(rankaddr | WL);
 		mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(3));
-		read32((u32 *)rankaddr);
+		read32p(rankaddr);
 		mchbar_clrsetbits32(DCC_MCHBAR, DCC_SET_EREG_MASK, DCC_SET_EREGx(1));
-		read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS));
+		read32p(rankaddr | ODT_120OHMS | ODS_34OHMS);
 		mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG);
-		read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED));
+		read32p(rankaddr | WR | DLL1 | CAS | INTERLEAVED);
 		mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_SET_MREG);
-		read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED));
+		read32p(rankaddr | WR | CAS | INTERLEAVED);
 	}
 }
 
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index be614aebff..d3571dfbd4 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -96,7 +96,7 @@ static int read_training_test(const int channel, const int lane,
 	for (i = 0; i < addresses->count; ++i) {
 		unsigned int offset;
 		for (offset = lane_offset; offset < 320; offset += 8) {
-			const u32 read = read32((u32 *)(addresses->addr[i] + offset));
+			const u32 read = read32p(addresses->addr[i] + offset);
 			const u32 good = read_training_schedule[offset >> 3];
 			if ((read & lane_mask) != (good & lane_mask))
 				return 0;
@@ -211,7 +211,7 @@ static void perform_read_training(const dimminfo_t *const dimms)
 			/* Write test pattern. */
 			unsigned int offset;
 			for (offset = 0; offset < 320; offset += 4)
-				write32((u32 *)(addresses.addr[i] + offset),
+				write32p(addresses.addr[i] + offset,
 					read_training_schedule[offset >> 3]);
 		}
 
@@ -419,18 +419,18 @@ static int write_training_test(const address_bunch_t *const addresses,
 		unsigned int off;
 		for (off = 0; off < 640; off += 8) {
 			const u32 pattern = write_training_schedule[off >> 3];
-			write32((u32 *)(addr + off), pattern);
-			write32((u32 *)(addr + off + 4), pattern);
+			write32p(addr + off, pattern);
+			write32p(addr + off + 4, pattern);
 		}
 
 		mchbar_setbits8(0x78, 1);
 
 		for (off = 0; off < 640; off += 8) {
 			const u32 good = write_training_schedule[off >> 3];
-			const u32 read1 = read32((u32 *)(addr + off));
+			const u32 read1 = read32p(addr + off);
 			if ((read1 & masks[0]) != (good & masks[0]))
 				goto _bad_timing_out;
-			const u32 read2 = read32((u32 *)(addr + off + 4));
+			const u32 read2 = read32p(addr + off + 4);
 			if ((read2 & masks[1]) != (good & masks[1]))
 				goto _bad_timing_out;
 		}
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index 1d207468a5..6ca801337f 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -128,7 +128,7 @@ static int read_dqs_level(const int channel, const int lane)
 	mchbar_setbits32(mchbar, 1 << 9);
 
 	/* Read from this channel. */
-	read32((u32 *)raminit_get_rank_addr(channel, 0));
+	read32p(raminit_get_rank_addr(channel, 0));
 
 	mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4);
 	return mchbar_read32(mchbar) & (1 << 30);