diff options
| author | Li, Jincheng <jincheng.li@intel.com> | 2023-03-01 18:25:49 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-03-26 10:14:23 +0000 |
| commit | 969f04fb345506621c5d1d6eb8dff558688285b5 (patch) | |
| tree | 8e6577b6b6a8a2840b41fc6e70cfe4cdc2f24313 | |
| parent | 31998020458af821cb61d0000ee2cbd0293958f6 (diff) | |
soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4
FSP2.4 and previous FSP versions have different FSP-T UPD
parameter settings.
Change-Id: I48384944ac69636cca2acd8169d3dd15f90362ec
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81313
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/xeon_sp/bootblock.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 62ca48f7c2..3e9922f6e9 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -14,6 +14,32 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> +#if (CONFIG(PLATFORM_USES_FSP2_4)) +const FSPT_UPD temp_ram_init_params = { + .FspUpdHeader = { + .Signature = FSPT_UPD_SIGNATURE, + .Revision = 2, + .Reserved = {0}, + }, + .FsptArchUpd = { + .Revision = 2, + .Length = 32, + .FspDebugHandler = 0, + .Reserved1 = {0}, + }, + .FsptCoreUpd = { + .MicrocodeRegionBase = 0, + .MicrocodeRegionLength = 0, + .CodeRegionBase = (UINT64)CACHE_ROM_BASE, + .CodeRegionLength = (UINT64)CACHE_ROM_SIZE, + }, + .FsptConfig = { + .FsptPort80RouteDisable = 0, + .ReservedTempRamInitUpd = {0}, + }, + .UpdTerminator = 0x55AA, +}; +#else const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { .Signature = FSPT_UPD_SIGNATURE, @@ -34,6 +60,7 @@ const FSPT_UPD temp_ram_init_params = { .UnusedUpdSpace0 = {0}, .UpdTerminator = 0x55AA, }; +#endif //(!CONFIG(PLATFORM_USES_FSP2_4)) static uint64_t assembly_timestamp; static uint64_t bootblock_timestamp; |