diff options
| author | Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> | 2022-12-12 15:23:19 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-16 17:05:22 +0000 |
| commit | 93197d20b65002fcd09fd9ed82f5c644aab0c352 (patch) | |
| tree | 9ade745e14c417f06ed8a668affda4a54c88cfc3 | |
| parent | 26a8dea551befff05ed1082c808851ee176291ec (diff) | |
mb/google/brya/var/marasov: Disable unused PCIE8 for s0ix
Disable unused PCIE8 for fix system can not enter S0ix completely.
BUG=b:261915226
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/marasov/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 63899cef23..832554e65c 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -182,6 +182,7 @@ chip soc/intel/alderlake device generic 0 on end end end + device ref pcie_rp8 off end device ref pcie_rp11 on # Enable NVMe SSD PCIe 11-12 using clk 1 register "pch_pcie_rp[PCH_RP(11)]" = "{ |