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authorReka Norman <rekanorman@google.com>2022-12-19 12:34:52 +1100
committerSubrata Banik <subratabanik@google.com>2023-01-06 10:39:45 +0000
commit91fe94ac9f646582b4007b05a983740784e7fa3c (patch)
tree1aee8b8278f03df2ba2dfa37f84141944eff7989
parent166c30309e99aa04aeb46658527b3e20899a451c (diff)
mb/google/nissa: Disable stage cache
Although S3 is supported on nissa, only S0ix is used on user devices, so we can ignore optimising the S3 resume time. Disable the stage cache to save boot time at the cost on increasing the S3 resume time. Boot time is reduced by ~6 ms. This is mostly from adding postcar to the stage cache, which is slow since TSEG is not cached in romstage. Adding ramstage and FSP-S take negligible time. The S3 resume time is increased by ~89 ms total from loading and decompressing ramstage and FSP-S. Boot time before: 3:after RAM initialization 573,295 (931) 4:end of romstage 583,569 (10,274) 100:start of postcar 587,729 (4,160) Boot time after: 3:after RAM initialization 571,527 (830) 4:end of romstage 575,712 (4,185) 100:start of postcar 579,866 (4,153) S3 resume time before: 101:end of postcar 368,904 (0) 10:start of ramstage 369,165 (260) 971:loading FSP-S 385,742 (16,577) 30:device enumeration 407,105 (21,362) S3 resume time after: 101:end of postcar 363,101 (0) 8:starting to load ramstage 363,101 (0) 15:starting LZMA decompress (ignore for x86) 382,802 (19,701) 16:finished LZMA decompress (ignore for x86) 431,620 (48,817) 9:finished loading ramstage 431,850 (230) 10:start of ramstage 431,927 (76) 971:loading FSP-S 448,357 (16,430) 17:starting LZ4 decompress (ignore for x86) 474,420 (26,062) 18:finished LZ4 decompress (ignore for x86) 474,627 (206) BUG=b:247940538, b:192032803 TEST=Boot and S3 suspend/resume on craask Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71677 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
-rw-r--r--src/mainboard/google/brya/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 9f0c223aa9..112c7df1c6 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -68,6 +68,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
select DRIVERS_INTEL_ISH
+ select MAINBOARD_DISABLE_STAGE_CACHE
select MEMORY_SOLDERDOWN
select SOC_INTEL_ALDERLAKE_PCH_N
select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW