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| author | Zheng Bao <fishbaozi@gmail.com> | 2023-04-07 10:51:20 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-11 13:22:33 +0000 |
| commit | 8cb14becbc15f19944a3b0f04c8dcfa44c554e3b (patch) | |
| tree | 63c9eefc37d5009cdc3d854016c08bd75d6da483 | |
| parent | 71a2a3d8fcf07465506a9f48790d424cf3b4bf39 (diff) | |
soc/amd: Add definition of SPI ROM remapping
Change-Id: Icafa36ae2e07068c276600067bba1d0377f0824b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74258
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/spi.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index dc7097f275..cf918143c7 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -70,6 +70,8 @@ enum spi100_speed { #define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) +#define SPI_ROM_PAGE 0x5c + #define SPI_FIFO 0x80 #define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */ #define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) |