diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-05-24 21:56:45 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-28 04:30:15 +0000 |
| commit | 83d341061e14bea04d64386e97c7e22b9a2c9727 (patch) | |
| tree | b7426b8aa6fd8e7076db8b528d29a970dcce5ba4 | |
| parent | 3c6b3040846a66f81615159c21e61208d90b3992 (diff) | |
mb/starlite/lite: Configure tcc_offset based on power_profile settings
Set tcc_offset value based on the power_profile value, ranging from 5
to 15 degrees.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id30bec9c095517884a7361226aed703b370f2207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
| -rw-r--r-- | src/mainboard/starlabs/lite/devtree.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c index 16bff732a4..221eb43c03 100644 --- a/src/mainboard/starlabs/lite/devtree.c +++ b/src/mainboard/starlabs/lite/devtree.c @@ -26,16 +26,19 @@ void devtree_update(void) /* Update PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - soc_conf->tdp_pl1_override = 6; - soc_conf->tdp_pl2_override = 10; + soc_conf->tdp_pl1_override = 6; + soc_conf->tdp_pl2_override = 10; + cfg->tcc_offset = 15; break; case PP_BALANCED: - soc_conf->tdp_pl1_override = 10; - soc_conf->tdp_pl2_override = 15; + soc_conf->tdp_pl1_override = 10; + soc_conf->tdp_pl2_override = 15; + cfg->tcc_offset = 10; break; case PP_PERFORMANCE: - soc_conf->tdp_pl1_override = 10; - soc_conf->tdp_pl2_override = 20; + soc_conf->tdp_pl1_override = 10; + soc_conf->tdp_pl2_override = 20; + cfg->tcc_offset = 5; break; } |