diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-02 18:06:21 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-11-02 17:31:55 +0000 |
| commit | 82689d2ac8057afcdb6f77b9ecb6e53120edbf61 (patch) | |
| tree | 7d4b0e16f2bfb8b365cd834429ab0a6e97beb44b | |
| parent | f78ade3e314c10e4452a67de027b35d000ab6609 (diff) | |
mb/google/volteer/var/volteer2: Merge `common_soc_config`
SCONFIG complains because of the duplicate devicetree entry.
Change-Id: Ibdd60efdbcee5bda7c570d4b98f29cc8ede584cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/mainboard/google/volteer/variants/volteer2/overridetree.cb | 34 |
1 files changed, 8 insertions, 26 deletions
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 6726830539..bb4db53e32 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -19,12 +19,20 @@ chip soc/intel/tigerlake #| I2C3 | Camera, SAR1 | #| I2C5 | Trackpad | #+-------------------+---------------------------+ + # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM + # communication, that one needs early initialization. register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, .i2c[1] = { .speed = I2C_SPEED_FAST, + .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), }, .i2c[2] = { .speed = I2C_SPEED_FAST, @@ -56,32 +64,6 @@ chip soc/intel/tigerlake register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" - # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM - # communication, that one needs early initialization. - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .gspi[0] = { - .speed_mhz = 1, - .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - device domain 0 on device ref dptf on chip drivers/intel/dptf |