diff options
| author | Martin Roth <martinroth@google.com> | 2017-10-16 14:55:53 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-20 17:48:49 +0000 |
| commit | 7eb363c505f26aa8cc0a30f5b6c0229ca8914489 (patch) | |
| tree | 1ccd715725f4160b5e2cb546af6581d6298233dd | |
| parent | c450fbe909e7ed1bc8309ace60ad45fc65a208e1 (diff) | |
Stoney Ridge Platforms: cast AGESA tables to void *
In the original AGESA headers, these tables are not defined as const.
Cast them to void * so that they'll work with either version of the
headers.
BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.
Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5 files changed, 9 insertions, 9 deletions
diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c index 6aebe4f988..8ab4240c16 100644 --- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c @@ -47,5 +47,5 @@ static const GPIO_CONTROL oem_gardenia_gpio[] = { void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio; + FchParams_reset->EarlyOemGpioTable = (void *)oem_gardenia_gpio; } diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c index 52148fdf0e..53b4a6ca04 100644 --- a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c +++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c @@ -102,8 +102,8 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .Flags = DESCRIPTOR_TERMINATE_LIST, .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList + .PciePortList = (void *)PortList, + .DdiLinkList = (void *)DdiList }; static const UINT32 AzaliaCodecAlc286Table[] = { @@ -150,7 +150,7 @@ static CONST CODEC_VERB_TABLE_LIST CodecTableList[] = { /*---------------------------------------------------------------------------*/ VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; InitEarly->PlatformConfig.AzaliaCodecVerbTable = (uint64_t)(uintptr_t)CodecTableList; } diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index 82f13d6e66..49f7190a4e 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -23,7 +23,7 @@ extern const GPIO_CONTROL oem_kahlee_gpio[]; void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { - FchParams_env->PostOemGpioTable = oem_kahlee_gpio; + FchParams_env->PostOemGpioTable = (void *)oem_kahlee_gpio; /* SDHCI/MMC configuration */ FchParams_env->Sd.SdSlotType = 1; // EMMC diff --git a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c index 73d129594d..3ca3c6f9e7 100644 --- a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c @@ -23,5 +23,5 @@ extern const GPIO_CONTROL oem_kahlee_gpio[]; void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio; + FchParams_reset->EarlyOemGpioTable = (void *)oem_kahlee_gpio; } diff --git a/src/mainboard/google/kahlee/bootblock/OemCustomize.c b/src/mainboard/google/kahlee/bootblock/OemCustomize.c index 38d08e553f..9530169edc 100644 --- a/src/mainboard/google/kahlee/bootblock/OemCustomize.c +++ b/src/mainboard/google/kahlee/bootblock/OemCustomize.c @@ -101,8 +101,8 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = { static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .Flags = DESCRIPTOR_TERMINATE_LIST, .SocketId = 0, - .PciePortList = PortList, - .DdiLinkList = DdiList + .PciePortList = (void *)PortList, + .DdiLinkList = (void *)DdiList }; /*---------------------------------------------------------------------------*/ @@ -123,7 +123,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { /*---------------------------------------------------------------------------*/ VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; } |