diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-07-16 09:49:53 +0200 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-07-17 22:01:20 +0000 |
| commit | 7d89264cdf7944004165ad79cb439803a73f4b49 (patch) | |
| tree | 4d25363c493f4ac848b9c25a3170d3cad793ddf0 | |
| parent | 644a67c1162a340303c8c800c30946c87e62ce4e (diff) | |
sb/amd/agesa: Fix some white spaces issues
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1497c7589570b8ff3873149a0fb212bad96ad432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/imc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/reset.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/resume.c | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 361989b270..b1a71f3f32 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -32,7 +32,7 @@ void imc_reg_init(void) UINT8 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 0x3, 0x1E4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0x3, 0x1E4); LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); PciData &= (UINT8)0x8F; PciData |= 0x10; diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index fd710ab861..2efc5bc2a5 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -244,7 +244,7 @@ static void hudson_lpc_enable_childrens_resources(struct device *dev) default: rsize = 0; /* try AGESA allocated region in region 0 */ - if ((var_num > 0) && ((base >=reg_var[0]) && + if ((var_num > 0) && ((base >= reg_var[0]) && ((base + res->size) <= (reg_var[0] + reg_size[0])))) rsize = reg_size[0]; } diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index 48751a4e64..fbb62c88fc 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -8,9 +8,9 @@ #include <reset.h> #define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#define HTIC_ColdR_Detect (1 << 4) +#define HTIC_BIOSR_Detect (1 << 5) +#define HTIC_INIT_Detect (1 << 6) void cf9_reset_prepare(void) { diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 9a6d2a247d..a742e22df9 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -98,7 +98,7 @@ static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams) int i; for (i = 0; i < sizeof(FchParams); i++) { - printk(BIOS_DEBUG, " %02x", ((u8 *) FchParams)[i]); + printk(BIOS_DEBUG, " %02x", ((u8 *)FchParams)[i]); if ((i % 16) == 15) printk(BIOS_DEBUG, "\n"); } |