diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-25 17:20:59 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-12 12:24:51 +0000 |
| commit | 7bc8fd58a323dba10d38867dc018a9feed2befaa (patch) | |
| tree | a9f5f7c9a722e562b408e22c8705ca9bed67f89c | |
| parent | cf46099979155659d9c5e781906764887c9c48c6 (diff) | |
mb/google/brya/acpi: Save/restore/clear some registers over GCOFF
Similar to the prior CL (commit db8ad5e), do the same register dance
before/after GCOFF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8fecba40c5a5af11e24f82db07face3ce10481bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67086
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/acpi/power.asl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl index ecd48e7a76..c9edf49162 100644 --- a/src/mainboard/google/brya/acpi/power.asl +++ b/src/mainboard/google/brya/acpi/power.asl @@ -294,6 +294,24 @@ Method (NPON, 0, Serialized) SRCC (SRCCLK_ENABLE) PGON () \_SB.PCI0.PEG0.LD23 () + + /* Wait for dGPU to reappear on the bus */ + Local0 = 50 + While (NVID != PCI_VID_NVIDIA) + { + Stall (100) + Local0-- + If (Local0 == 0) + { + Break + } + } + + /* Restore the PEG LTR enable bit */ + LREN = SLTR + + /* Clear recoverable errors detected bit */ + CEDR = 1 } } @@ -312,6 +330,8 @@ Method (NPOF, 0, Serialized) } Else { + /* Save the PEG port's LTR setting */ + SLTR = LREN \_SB.PCI0.PEG0.DL23 () PGOF () SRCC (SRCCLK_DISABLE) |