diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-07-26 21:33:45 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-28 09:47:12 +0000 |
| commit | 7b7581f1207c919bcb50e1ea2b2300dff093fa40 (patch) | |
| tree | bdcc5a45387304bcda92c760f63799826c01a4f8 | |
| parent | 250a7ac1f5045c9aa59fd26fe9e014eb42c80242 (diff) | |
mb/prodrive/hermes: Relocate device enable options
Since there aren't any other variants, we can move things between the
devicetree and the overridetree.
Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change.
Change-Id: I54aac67237a3850dbf11f58bd41aba87505214f3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43927
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/prodrive/hermes/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb | 10 |
2 files changed, 6 insertions, 8 deletions
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 0491236e1b..1ed15a6882 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -25,7 +25,9 @@ chip soc/intel/cannonlake device pci 14.2 on end # RAM controller device pci 14.5 off end # SDCard - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end device pci 16.1 on end # Management Engine Interface 2 device pci 16.4 on end # Management Engine Interface 3 device pci 17.0 on end # SATA diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 6c6fe2d941..532ab9f3c8 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -131,12 +131,6 @@ chip soc/intel/cannonlake # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" - # HECI - register "HeciEnabled" = "1" - - # Internal GFX - register "InternalGfx" = "1" - # Disable S0ix register "s0ix_enable" = "0" @@ -171,7 +165,9 @@ chip soc/intel/cannonlake device domain 0 on - device pci 02.0 on end # Integrated Graphics Device + device pci 02.0 on # Integrated Graphics Device + register "InternalGfx" = "1" + end chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" device pci 14.3 on end # CNVi wifi |