diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-04-25 05:41:16 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-04-29 15:40:07 +0000 |
| commit | 78439118c8263160818bc5a2cb68f7a8be0e5a26 (patch) | |
| tree | 503f6e7505862ee2dac454e929249ac1e2719396 | |
| parent | b84d55b582d0cd48078f039b0b5ea4e8896189e5 (diff) | |
soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP
In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.
Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
| -rw-r--r-- | src/soc/intel/xeon_sp/lockdown.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 9e25920011..a3d17b46c3 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/cfg.h> #include <intelblocks/lpc_lib.h> #include <intelpch/lockdown.h> #include <soc/lockdown.h> @@ -20,6 +21,9 @@ static void lpc_lockdown_config(void) void soc_lockdown_config(int chipset_lockdown) { + if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP) + return; + lpc_lockdown_config(); pmc_lockdown_config(); sata_lockdown_config(chipset_lockdown); |