UART 8250: Unconditionally provide register constants and use UART8250 prefix.

The register indexes and bitfield masks were guarded by the UART8250 config
options, but it might be (is) necessary to use them in a driver that is
UART8250 like without actually using the 8250 driver itself. To avoid any name
collision with other drivers, also change the constant prefix from UART_ to
UART8250_.

Change-Id: Ie606d9e0329132961c3004688176204a829569dc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171336
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit a93900be8d8a8260db49e30737608f9161fbf249)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6715
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

5 files changed, 102 insertions, 102 deletions

diff --git a/src/console/Kconfig b/src/console/Kconfig
index 8a2da1c5e5..054177f486 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -48,7 +48,7 @@ config UART_FOR_CONSOLE
 # program different LDN to actually change the physical port.
 config TTYS0_BASE
 	hex
-	depends on DRIVERS_UART_8250IO
+	depends on DRIVERS_UART
 	default 0x3f8 if UART_FOR_CONSOLE = 0
 	default 0x2f8 if UART_FOR_CONSOLE = 1
 	default 0x3e8 if UART_FOR_CONSOLE = 2
diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c
index feccc8232f..407bd863aa 100644
--- a/src/cpu/allwinner/a10/uart.c
+++ b/src/cpu/allwinner/a10/uart.c
@@ -22,19 +22,19 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
 	div = (u16) uart_baudrate_divisor(baud_rate,
 		uart_platform_refclk(), 16);
 	/* Enable access to Divisor Latch register */
-	write32(UART_LCR_DLAB, &uart->lcr);
+	write32(UART8250_LCR_DLAB, &uart->lcr);
 	/* Set baudrate */
 	write32((div >> 8) & 0xff, &uart->dlh);
 	write32(div & 0xff, &uart->dll);
 	/* Set line control */
-	reg32 = (data_bits - 5) & UART_LCR_WLS_MSK;
+	reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK;
 	switch (parity) {
 	case UART_PARITY_ODD:
-		reg32 |= UART_LCR_PEN;
+		reg32 |= UART8250_LCR_PEN;
 		break;
 	case UART_PARITY_EVEN:
-		reg32 |= UART_LCR_PEN;
-		reg32 |= UART_LCR_EPS;
+		reg32 |= UART8250_LCR_PEN;
+		reg32 |= UART8250_LCR_EPS;
 		break;
 	case UART_PARITY_NONE:	/* Fall through */
 	default:
@@ -45,7 +45,7 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
 
 static void a10_uart_enable_fifos(struct a10_uart *uart)
 {
-	write32(UART_FCR_FIFO_EN, &uart->fcr);
+	write32(UART8250_FCR_FIFO_EN, &uart->fcr);
 }
 
 static int tx_fifo_full(struct a10_uart *uart)
@@ -54,12 +54,12 @@ static int tx_fifo_full(struct a10_uart *uart)
 	 * that the TX register is empty, not that the FIFO is not full, but
 	 * this may be due to a datasheet typo. Keep the current name to signal
 	 * intent. */
-	return !(read32(&uart->lsr) & UART_LSR_THRE);
+	return !(read32(&uart->lsr) & UART8250_LSR_THRE);
 }
 
 static int rx_fifo_empty(struct a10_uart *uart)
 {
-	return !(read32(&uart->lsr) & UART_LSR_DR);
+	return !(read32(&uart->lsr) & UART8250_LSR_DR);
 }
 
 /**
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index f4a7b0ab74..f4f4d010a5 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -48,25 +48,25 @@
 
 static int uart8250_can_tx_byte(unsigned base_port)
 {
-	return inb(base_port + UART_LSR) & UART_LSR_THRE;
+	return inb(base_port + UART8250_LSR) & UART8250_LSR_THRE;
 }
 
 static void uart8250_tx_byte(unsigned base_port, unsigned char data)
 {
 	unsigned long int i = SINGLE_CHAR_TIMEOUT;
 	while (i-- && !uart8250_can_tx_byte(base_port));
-	outb(data, base_port + UART_TBR);
+	outb(data, base_port + UART8250_TBR);
 }
 
 static void uart8250_tx_flush(unsigned base_port)
 {
 	unsigned long int i = FIFO_TIMEOUT;
-	while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT));
+	while (i-- && !(inb(base_port + UART8250_LSR) & UART8250_LSR_TEMT));
 }
 
 static int uart8250_can_rx_byte(unsigned base_port)
 {
-	return inb(base_port + UART_LSR) & UART_LSR_DR;
+	return inb(base_port + UART8250_LSR) & UART8250_LSR_DR;
 }
 
 static unsigned char uart8250_rx_byte(unsigned base_port)
@@ -75,7 +75,7 @@ static unsigned char uart8250_rx_byte(unsigned base_port)
 	while (i-- && !uart8250_can_rx_byte(base_port));
 
 	if (i)
-		return inb(base_port + UART_RBR);
+		return inb(base_port + UART8250_RBR);
 	else
 		return 0x0;
 }
@@ -84,22 +84,22 @@ static void uart8250_init(unsigned base_port, unsigned divisor)
 {
 	DISABLE_TRACE;
 	/* Disable interrupts */
-	outb(0x0, base_port + UART_IER);
+	outb(0x0, base_port + UART8250_IER);
 	/* Enable FIFOs */
-	outb(UART_FCR_FIFO_EN, base_port + UART_FCR);
+	outb(UART8250_FCR_FIFO_EN, base_port + UART8250_FCR);
 
 	/* assert DTR and RTS so the other end is happy */
-	outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR);
+	outb(UART8250_MCR_DTR | UART8250_MCR_RTS, base_port + UART8250_MCR);
 
 	/* DLAB on */
-	outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR);
+	outb(UART8250_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART8250_LCR);
 
 	/* Set Baud Rate Divisor. 12 ==> 9600 Baud */
-	outb(divisor & 0xFF,   base_port + UART_DLL);
-	outb((divisor >> 8) & 0xFF,    base_port + UART_DLM);
+	outb(divisor & 0xFF,   base_port + UART8250_DLL);
+	outb((divisor >> 8) & 0xFF,    base_port + UART8250_DLM);
 
 	/* Set to 3 for 8N1 */
-	outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
+	outb(CONFIG_TTYS0_LCS, base_port + UART8250_LCR);
 	ENABLE_TRACE;
 }
 
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index 976bcb6949..79654f1786 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -35,7 +35,7 @@
 
 static int uart8250_mem_can_tx_byte(unsigned base_port)
 {
-	return read8(base_port + UART_LSR) & UART_LSR_THRE;
+	return read8(base_port + UART8250_LSR) & UART8250_LSR_THRE;
 }
 
 static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
@@ -43,19 +43,19 @@ static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
 	unsigned long int i = SINGLE_CHAR_TIMEOUT;
 	while(i-- && !uart8250_mem_can_tx_byte(base_port))
 		udelay(1);
-	write8(base_port + UART_TBR, data);
+	write8(base_port + UART8250_TBR, data);
 }
 
 static void uart8250_mem_tx_flush(unsigned base_port)
 {
 	unsigned long int i = FIFO_TIMEOUT;
-	while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT))
+	while(i-- && !(read8(base_port + UART8250_LSR) & UART8250_LSR_TEMT))
 		udelay(1);
 }
 
 static int uart8250_mem_can_rx_byte(unsigned base_port)
 {
-	return read8(base_port + UART_LSR) & UART_LSR_DR;
+	return read8(base_port + UART8250_LSR) & UART8250_LSR_DR;
 }
 
 static unsigned char uart8250_mem_rx_byte(unsigned base_port)
@@ -64,7 +64,7 @@ static unsigned char uart8250_mem_rx_byte(unsigned base_port)
 	while(i-- && !uart8250_mem_can_rx_byte(base_port))
 		udelay(1);
 	if (i)
-		return read8(base_port + UART_RBR);
+		return read8(base_port + UART8250_RBR);
 	else
 		return 0x0;
 }
@@ -72,21 +72,21 @@ static unsigned char uart8250_mem_rx_byte(unsigned base_port)
 static void uart8250_mem_init(unsigned base_port, unsigned divisor)
 {
 	/* Disable interrupts */
-	write8(base_port + UART_IER, 0x0);
+	write8(base_port + UART8250_IER, 0x0);
 	/* Enable FIFOs */
-	write8(base_port + UART_FCR, UART_FCR_FIFO_EN);
+	write8(base_port + UART8250_FCR, UART8250_FCR_FIFO_EN);
 
 	/* Assert DTR and RTS so the other end is happy */
-	write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
+	write8(base_port + UART8250_MCR, UART8250_MCR_DTR | UART8250_MCR_RTS);
 
 	/* DLAB on */
-	write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS);
+	write8(base_port + UART8250_LCR, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS);
 
-	write8(base_port + UART_DLL, divisor & 0xFF);
-	write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);
+	write8(base_port + UART8250_DLL, divisor & 0xFF);
+	write8(base_port + UART8250_DLM, (divisor >> 8) & 0xFF);
 
 	/* Set to 3 for 8N1 */
-	write8(base_port + UART_LCR, CONFIG_TTYS0_LCS);
+	write8(base_port + UART8250_LCR, CONFIG_TTYS0_LCS);
 }
 
 void uart_init(int idx)
diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h
index cdfbb1bc20..2720b8db10 100644
--- a/src/drivers/uart/uart8250reg.h
+++ b/src/drivers/uart/uart8250reg.h
@@ -21,88 +21,88 @@
 #define UART8250REG_H
 
 /* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
+#define UART8250_RBR 0x00
+#define UART8250_TBR 0x00
 
 /* Control */
-#define UART_IER 0x01
-#define   UART_IER_MSI		0x08 /* Enable Modem status interrupt */
-#define   UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
-#define   UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
-#define   UART_IER_RDI		0x01 /* Enable receiver data interrupt */
+#define UART8250_IER 0x01
+#define   UART8250_IER_MSI	0x08 /* Enable Modem status interrupt */
+#define   UART8250_IER_RLSI	0x04 /* Enable receiver line status interrupt */
+#define   UART8250_IER_THRI	0x02 /* Enable Transmitter holding register int. */
+#define   UART8250_IER_RDI	0x01 /* Enable receiver data interrupt */
 
-#define UART_IIR 0x02
-#define   UART_IIR_NO_INT	0x01 /* No interrupts pending */
-#define   UART_IIR_ID		0x06 /* Mask for the interrupt ID */
+#define UART8250_IIR 0x02
+#define   UART8250_IIR_NO_INT	0x01 /* No interrupts pending */
+#define   UART8250_IIR_ID	0x06 /* Mask for the interrupt ID */
 
-#define   UART_IIR_MSI		0x00 /* Modem status interrupt */
-#define   UART_IIR_THRI		0x02 /* Transmitter holding register empty */
-#define   UART_IIR_RDI		0x04 /* Receiver data interrupt */
-#define   UART_IIR_RLSI		0x06 /* Receiver line status interrupt */
+#define   UART8250_IIR_MSI	0x00 /* Modem status interrupt */
+#define   UART8250_IIR_THRI	0x02 /* Transmitter holding register empty */
+#define   UART8250_IIR_RDI	0x04 /* Receiver data interrupt */
+#define   UART8250_IIR_RLSI	0x06 /* Receiver line status interrupt */
 
-#define UART_FCR 0x02
-#define   UART_FCR_FIFO_EN	0x01 /* Fifo enable */
-#define   UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-#define   UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
-#define   UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
-#define   UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
-#define   UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
-#define   UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
-#define   UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
-#define   UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
+#define UART8250_FCR 0x02
+#define   UART8250_FCR_FIFO_EN		0x01 /* Fifo enable */
+#define   UART8250_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define   UART8250_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define   UART8250_FCR_DMA_SELECT	0x08 /* For DMA applications */
+#define   UART8250_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define   UART8250_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define   UART8250_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define   UART8250_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define   UART8250_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
 
-#define   UART_FCR_RXSR		0x02 /* Receiver soft reset */
-#define   UART_FCR_TXSR		0x04 /* Transmitter soft reset */
+#define   UART8250_FCR_RXSR		0x02 /* Receiver soft reset */
+#define   UART8250_FCR_TXSR		0x04 /* Transmitter soft reset */
 
-#define UART_LCR 0x03
-#define   UART_LCR_WLS_MSK	0x03 /* character length select mask */
-#define   UART_LCR_WLS_5	0x00 /* 5 bit character length */
-#define   UART_LCR_WLS_6	0x01 /* 6 bit character length */
-#define   UART_LCR_WLS_7	0x02 /* 7 bit character length */
-#define   UART_LCR_WLS_8	0x03 /* 8 bit character length */
-#define   UART_LCR_STB		0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define   UART_LCR_PEN		0x08 /* Parity enable */
-#define   UART_LCR_EPS		0x10 /* Even Parity Select */
-#define   UART_LCR_STKP		0x20 /* Stick Parity */
-#define   UART_LCR_SBRK		0x40 /* Set Break */
-#define   UART_LCR_BKSE		0x80 /* Bank select enable */
-#define   UART_LCR_DLAB		0x80 /* Divisor latch access bit */
+#define UART8250_LCR 0x03
+#define   UART8250_LCR_WLS_MSK	0x03 /* character length select mask */
+#define   UART8250_LCR_WLS_5	0x00 /* 5 bit character length */
+#define   UART8250_LCR_WLS_6	0x01 /* 6 bit character length */
+#define   UART8250_LCR_WLS_7	0x02 /* 7 bit character length */
+#define   UART8250_LCR_WLS_8	0x03 /* 8 bit character length */
+#define   UART8250_LCR_STB	0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define   UART8250_LCR_PEN	0x08 /* Parity enable */
+#define   UART8250_LCR_EPS	0x10 /* Even Parity Select */
+#define   UART8250_LCR_STKP	0x20 /* Stick Parity */
+#define   UART8250_LCR_SBRK	0x40 /* Set Break */
+#define   UART8250_LCR_BKSE	0x80 /* Bank select enable */
+#define   UART8250_LCR_DLAB	0x80 /* Divisor latch access bit */
 
-#define UART_MCR 0x04
-#define   UART_MCR_DTR		0x01 /* DTR   */
-#define   UART_MCR_RTS		0x02 /* RTS   */
-#define   UART_MCR_OUT1		0x04 /* Out 1 */
-#define   UART_MCR_OUT2		0x08 /* Out 2 */
-#define   UART_MCR_LOOP		0x10 /* Enable loopback test mode */
+#define UART8250_MCR 0x04
+#define   UART8250_MCR_DTR	0x01 /* DTR   */
+#define   UART8250_MCR_RTS	0x02 /* RTS   */
+#define   UART8250_MCR_OUT1	0x04 /* Out 1 */
+#define   UART8250_MCR_OUT2	0x08 /* Out 2 */
+#define   UART8250_MCR_LOOP	0x10 /* Enable loopback test mode */
 
-#define UART_MCR_DMA_EN		0x04
-#define UART_MCR_TX_DFR		0x08
+#define UART8250_MCR_DMA_EN	0x04
+#define UART8250_MCR_TX_DFR	0x08
 
-#define UART_DLL 0x00
-#define UART_DLM 0x01
+#define UART8250_DLL 0x00
+#define UART8250_DLM 0x01
 
 /* Status */
-#define UART_LSR 0x05
-#define   UART_LSR_DR		0x01 /* Data ready */
-#define   UART_LSR_OE		0x02 /* Overrun */
-#define   UART_LSR_PE		0x04 /* Parity error */
-#define   UART_LSR_FE		0x08 /* Framing error */
-#define   UART_LSR_BI		0x10 /* Break */
-#define   UART_LSR_THRE		0x20 /* Xmit holding register empty */
-#define   UART_LSR_TEMT		0x40 /* Xmitter empty */
-#define   UART_LSR_ERR		0x80 /* Error */
+#define UART8250_LSR 0x05
+#define   UART8250_LSR_DR	0x01 /* Data ready */
+#define   UART8250_LSR_OE	0x02 /* Overrun */
+#define   UART8250_LSR_PE	0x04 /* Parity error */
+#define   UART8250_LSR_FE	0x08 /* Framing error */
+#define   UART8250_LSR_BI	0x10 /* Break */
+#define   UART8250_LSR_THRE	0x20 /* Xmit holding register empty */
+#define   UART8250_LSR_TEMT	0x40 /* Xmitter empty */
+#define   UART8250_LSR_ERR	0x80 /* Error */
 
-#define UART_MSR 0x06
-#define   UART_MSR_DCD		0x80 /* Data Carrier Detect */
-#define   UART_MSR_RI		0x40 /* Ring Indicator */
-#define   UART_MSR_DSR		0x20 /* Data Set Ready */
-#define   UART_MSR_CTS		0x10 /* Clear to Send */
-#define   UART_MSR_DDCD		0x08 /* Delta DCD */
-#define   UART_MSR_TERI		0x04 /* Trailing edge ring indicator */
-#define   UART_MSR_DDSR		0x02 /* Delta DSR */
-#define   UART_MSR_DCTS		0x01 /* Delta CTS */
+#define UART8250_MSR 0x06
+#define   UART8250_MSR_DCD	0x80 /* Data Carrier Detect */
+#define   UART8250_MSR_RI	0x40 /* Ring Indicator */
+#define   UART8250_MSR_DSR	0x20 /* Data Set Ready */
+#define   UART8250_MSR_CTS	0x10 /* Clear to Send */
+#define   UART8250_MSR_DDCD	0x08 /* Delta DCD */
+#define   UART8250_MSR_TERI	0x04 /* Trailing edge ring indicator */
+#define   UART8250_MSR_DDSR	0x02 /* Delta DSR */
+#define   UART8250_MSR_DCTS	0x01 /* Delta CTS */
 
-#define UART_SCR 0x07
-#define UART_SPR 0x07
+#define UART8250_SCR 0x07
+#define UART8250_SPR 0x07
 
 #endif /* UART8250REG_H */