diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-28 18:32:54 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-15 11:22:58 +0000 |
| commit | 6d2d19de7453de04830163a234a970ea9eab386c (patch) | |
| tree | acc385d66f03a7afe79479476a4b0af41d90a2f4 | |
| parent | 8832de380d3e53f556c1b04818f324ea1ac1d415 (diff) | |
mb/intel/baskingridge: Replace invalid C-state values
Basking Ridge is not ULT, thus does not support C-states deeper than C7.
Replace them with the values used by all other Haswell non-ULT boards to
allow subsequent commits to cleanly factor them out of the devicetree.
Change-Id: Ife34f7828f9ef19c8fccb3ac7b60146960112a81
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46907
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/intel/baskingridge/devicetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 784c926d5f..797230c8f1 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -17,13 +17,13 @@ chip northbridge/intel/haswell # Magic APIC ID to locate this chip device lapic 0xACAC off end - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "9" # ACPI(C3) = MWAIT(C7S) + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "9" # ACPI(C3) = MWAIT(C7S) + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" end end |