diff options
| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-28 03:56:52 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-28 03:56:52 +0000 |
| commit | 6bdc83bf5e76aa0b36cb5f52c11544091d71770b (patch) | |
| tree | 474451adb296e64baca29784ddf7bc87653b50d7 | |
| parent | 061c89e15d336b92b1e9fb2f9866c32f6496fb09 (diff) | |
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/cpu/amd/model_10xxx/fidvid.c | 2 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 5 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 1 |
3 files changed, 3 insertions, 5 deletions
diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index e1ee71a5a7..bbcfa28e06 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -738,7 +738,7 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid) } -static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid) +static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid) { u32 send; diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index c21a13551c..a256f9c508 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -157,7 +157,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) } #if CONFIG_SET_FIDVID -static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid); +static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid); #endif static inline __attribute__ ((always_inline)) @@ -346,8 +346,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) printk(BIOS_DEBUG, "init_fidvid_ap(stage1) apicid: %02x\n", apicid); - init_fidvid_ap(bsp_apicid, apicid, id.nodeid, - id.coreid); + init_fidvid_ap(apicid, id.nodeid, id.coreid); } } #endif diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 6f03be886d..566e1fbbb0 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -58,7 +58,6 @@ #define PS_NB_VID_SHFT 25 /* P-state bit shift for NbVid */ #define PS_BOTH_VID_OFF 0x01ff01ff /* Mask NbVid & CpuVid */ #define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */ -#define PS_NB_VID_SHFT 25 /* P-state NBVID shift */ #define PS_DIS 0x7fffffff /* disable P-state reg */ #define PS_EN 0x80000000 /* enable P-state reg */ #define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid] |