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authorSean Rhodes <sean@starlabs.systems>2023-04-17 20:29:45 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2023-04-20 20:44:21 +0000
commit6bb11a3e6c60dd9c88946ebe8e7475a15febf077 (patch)
tree178883cb5b705066b01d6e310e67981930bcf9c4
parent2980e317e3be99eef527a0578ae3a3982b2ccf40 (diff)
soc/intel/alderlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
Remove the `TcssD3ColdDisable` option in devicetree, as it exists in Kconfig. The setting is currently unused. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2590e8dec0a308e0dc3d467cb3dd2bb97e877492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74477 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/alderlake/chip.h2
-rw-r--r--src/soc/intel/alderlake/fsp_params.c2
2 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index b6fc43d287..c4662123d0 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -275,8 +275,6 @@ struct soc_intel_alderlake_config {
int s0ix_enable;
/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
uint8_t tcss_d3_hot_disable;
- /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
- uint8_t tcss_d3_cold_disable;
/* Enable DPTF support */
int dptf_enable;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 704f910a69..7789cec747 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -648,7 +648,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
/* D3Hot and D3Cold for TCSS */
s_cfg->D3HotEnable = !config->tcss_d3_hot_disable;
- s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT) && !config->tcss_d3_cold_disable;
+ s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT);
s_cfg->UsbTcPortEn = 0;
for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {