diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-09 11:19:29 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-10 19:00:34 +0000 |
| commit | 6ba1fcac3402a8719b6d080eb78e67b059a9b2ad (patch) | |
| tree | c2b4f8d899afa378e521c64c8aae4af157eb7d59 | |
| parent | 4f1147b54124609284e390b9a1176a90877848f5 (diff) | |
soc/amd/cezanne: Add SPI registers
These are identical to picasso.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/lpc.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/include/soc/lpc.h b/src/soc/amd/cezanne/include/soc/lpc.h new file mode 100644 index 0000000000..fcdcd96939 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/lpc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_LPC_H +#define AMD_CEZANNE_LPC_H + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(8) +#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) +#define PSP_SPI_MMIO_SEL BIT(4) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4)) + +#endif /* AMD_CEZANNE_LPC_H */ |