diff options
| author | Johnny Lin <johnny_lin@wiwynn.com> | 2022-01-24 15:18:57 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-01-08 01:32:28 +0000 |
| commit | 6b1e7dd06187789852f35ed6a658bd608803c30c (patch) | |
| tree | 12eb8c06b1e6bf66f1b392c22a1ca0ccb93aba70 | |
| parent | 43b0ed708963110368d6cf1a048f79d3a09817ea (diff) | |
soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCO
Also disable TCO timer through calling tco_configure().
If tco_configure() is not called, the TCO timeout would
trigger SMI periodically about every 2 seconds with SMM log:
"TCO_STS: BIT18 TIMEOUT"
Tested=On AC CRB, does not see periodic SMI log.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I2d307ad16109ae11862dd5e5acc0f12f47b22582
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/bootblock.c | 4 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 91b156956d..784fd2e250 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -47,12 +47,13 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SMM - select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_TCO select SOC_INTEL_COMMON_PCH_SERVER select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 5ea09ac3a7..ba215d8f84 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -4,6 +4,7 @@ #include <device/pci.h> #include <FsptUpd.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/tco.h> #include <soc/iomap.h> #include <console/console.h> #include <cpu/x86/mtrr.h> @@ -73,4 +74,7 @@ void bootblock_soc_init(void) intel_cbnt_log_registers(); bootblock_pch_init(); + + /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ + tco_configure(); } |