diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-05 09:24:53 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-05 22:02:04 +0100 |
| commit | 59bff09f301fe3544cc70aafaf666cae40fa3257 (patch) | |
| tree | a76b8c31b48a418121cfa0f20e5241f799a5a148 | |
| parent | 1df7064e0dabfe41fe4fd87789f24b703d07b2c8 (diff) | |
fsp_baytrail: Update function disable code
- The EDS has the function disable bit for eMMC incorrectly listed
as 8. Changing it back to the correct bit 11.
- The FSP will disable functions that it is told are disabled, so
coreboot code that disables the functions is redundant. Removing it.
Change-Id: I95c31d92d3af5182ddf7fd47f651bbb61cdedb82
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7653
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
| -rw-r--r-- | src/soc/intel/fsp_baytrail/baytrail/pmc.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/southcluster.c | 48 |
2 files changed, 1 insertions, 51 deletions
diff --git a/src/soc/intel/fsp_baytrail/baytrail/pmc.h b/src/soc/intel/fsp_baytrail/baytrail/pmc.h index ee15dd92a7..df6355a3df 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/pmc.h +++ b/src/soc/intel/fsp_baytrail/baytrail/pmc.h @@ -83,11 +83,9 @@ # define HSUART1_DIS (1 << 3) # define HSUART2_DIS (1 << 4) # define SPI_DIS (1 << 5) -# define MMC45_DIS (1 << 8) -# define EMMC_DIS (1 << 8) # define SDIO_DIS (1 << 9) # define SD_DIS (1 << 10) -# define MIPI_DIS (1 << 11) +# define MMC_DIS (1 << 11) # define HDA_DIS (1 << 12) # define LPE_DIS (1 << 13) # define OTG_DIS (1 << 14) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 2216902d6c..d87935b517 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -424,44 +424,10 @@ static void sc_disable_devfn(device_t dev) fd2_mask |= name_ ## _DIS switch (dev->path.pci.devfn) { - SET_DIS_MASK(MIPI); - break; - SET_DIS_MASK(EMMC); - break; - SET_DIS_MASK(SDIO); - break; - SET_DIS_MASK(SD); - break; - SET_DIS_MASK(SATA); - break; - SET_DIS_MASK(XHCI); - /* Disable super speed PHY when XHCI is not available. */ - fd2_mask |= USH_SS_PHY_DIS; - break; SET_DIS_MASK(LPE); break; - SET_DIS_MASK(MMC45); - break; - SET_DIS_MASK(SIO_DMA1); - break; - SET_DIS_MASK(I2C1); - break; - SET_DIS_MASK(I2C2); - break; - SET_DIS_MASK(I2C3); - break; - SET_DIS_MASK(I2C4); - break; - SET_DIS_MASK(I2C5); - break; - SET_DIS_MASK(I2C6); - break; - SET_DIS_MASK(I2C7); - break; SET_DIS_MASK(TXE); break; - SET_DIS_MASK(HDA); - break; SET_DIS_MASK(PCIE_PORT1); break; SET_DIS_MASK(PCIE_PORT2); @@ -470,20 +436,6 @@ static void sc_disable_devfn(device_t dev) break; SET_DIS_MASK(PCIE_PORT4); break; - SET_DIS_MASK(EHCI); - break; - SET_DIS_MASK(SIO_DMA2); - break; - SET_DIS_MASK(PWM1); - break; - SET_DIS_MASK(PWM2); - break; - SET_DIS_MASK(HSUART1); - break; - SET_DIS_MASK(HSUART2); - break; - SET_DIS_MASK(SPI); - break; SET_DIS_MASK2(SMBUS); break; SET_DIS_MASK(OTG); |