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authorRaul E Rangel <rrangel@chromium.org>2021-07-23 16:43:18 -0600
committerPatrick Georgi <pgeorgi@google.com>2021-11-02 08:18:29 +0000
commit55fea11f2ff5d2c8880dfe66c07bfb39c63affb0 (patch)
tree7f42a13439ad5c2b9348395ad8b7de91f1f4e2bd
parentfab6e44a95e8217818254d69de4ba648bfa9e8ed (diff)
soc/amd/common/block/cpu: Add support for cbfs_cache region
This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
-rw-r--r--src/soc/amd/common/block/cpu/Kconfig5
-rw-r--r--src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld9
2 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig
index 11b6c8ccdb..3dd1e33056 100644
--- a/src/soc/amd/common/block/cpu/Kconfig
+++ b/src/soc/amd/common/block/cpu/Kconfig
@@ -24,6 +24,11 @@ config MEMLAYOUT_LD_FILE
string
default "src/soc/amd/common/block/cpu/noncar/memlayout.ld"
+config CBFS_CACHE_SIZE
+ hex
+ help
+ The size of the cbfs_cache region.
+
config PAYLOAD_PRELOAD_CACHE_SIZE
hex
default 0x30000
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index 005bde093b..a542b7d6ad 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -25,6 +25,10 @@ BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE;
* | |
* reserved_dram_end +--------------------------------+
* | |
+ * | cbfs_cache (if reqd) |
+ * | (CBFS_CACHE_SIZE) |
+ * +--------------------------------+ VERSTAGE_ADDR + VERSTAGE_SIZE
+ * | |
* | verstage (if reqd) |
* | (VERSTAGE_SIZE) |
* +--------------------------------+ VERSTAGE_ADDR
@@ -95,6 +99,11 @@ SECTIONS
VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE)
#endif
+#if CONFIG_CBFS_CACHE_SIZE > 0
+ . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
+ CBFS_CACHE(., CONFIG_CBFS_CACHE_SIZE)
+#endif
+
EARLY_RESERVED_DRAM_END(.)
#if CONFIG(PAYLOAD_PRELOAD)