diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 23:03:13 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 00:28:14 +0000 |
| commit | 4d6c39d4f41b4d7dbfbb1df04390ccafbc487b42 (patch) | |
| tree | 4a44d39c22b271e61c316439513fbeb3dc5be1b1 | |
| parent | 78381094b20d1af933f369505910b4f5f2954895 (diff) | |
soc/amd/picasso/acpi: rename sb_fch.asl to mmio.asl
This file only contain the ACPI code describing the MMIO devices in the
FCH, so rename it to mmio.asl. This also brings the Picasso ACPI code a
bit more in line with the ACPI code of the newer SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I64490ba8e34ae1fbe6aea1ab6496b5b04ac4d0aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75591
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/picasso/acpi/mmio.asl (renamed from src/soc/amd/picasso/acpi/sb_fch.asl) | 0 | ||||
| -rw-r--r-- | src/soc/amd/picasso/acpi/soc.asl | 4 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/mmio.asl index c229284eb0..c229284eb0 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/mmio.asl diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index 0b520e42a9..a958570905 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -19,8 +19,8 @@ Scope(PCI0) { /* Describe PCI INT[A-H] for the Southbridge */ #include <soc/amd/common/acpi/pci_int.asl> -/* Describe the devices in the Southbridge */ -#include "sb_fch.asl" +/* Describe the MMIO devices in the FCH */ +#include "mmio.asl" /* Add GPIO library */ #include <soc/amd/common/acpi/gpio_bank_lib.asl> |