diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2023-03-27 11:33:32 +0100 |
|---|---|---|
| committer | Jakub Czapiga <jacz@semihalf.com> | 2023-04-12 12:25:13 +0000 |
| commit | 4d3a0266ce9f3c6ef8c26aa7ebb60d3be2436359 (patch) | |
| tree | afa0693f6726b403690cf20ddafd32d35d6f4763 | |
| parent | aaab6566c0a831245a1f4d90efb55fa55ab3a319 (diff) | |
mb/starlabs/starbook/adl: Fix OC pin config
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1c4bdab44f0d73546f52614917dccbe71f0911a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/starlabs/starbook/variants/adl/devicetree.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index c43f6a6eba..5c54f4da35 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -52,22 +52,22 @@ chip soc/intel/alderlake device ref crashlog off end device ref xhci on # Motherboard USB Type C - register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[0]" = "USB2_PORT_MID(OC5)" register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Motherboard USB 3.0 - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # Daughterboard USB 3.0 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Internal Webcam register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint Reader - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Daughterboard SD Card register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" |