mb/dell: Add Latitude E6400

Mainboard name is Compal JBL00. This is based on the GM45/ICH9M chipset
and uses DDR2 RAM. The EC is a SMSC MEC5035 which has internal flash, so
there's no issue about making sure to include the EC firmware in the
BIOS region. This only supports the variant with integrated graphics
only, the version with a discrete Nvidia Quadro NVS 160M is not
supported.
This port was based on the Lenovo T400 port.

Working:
- USB EHCI debug (lower USB port on right side)
- Keyboard
- Touchpad/trackpoint
- VGA
- Displayport
- ExpressCard
- Audio
- Ethernet
- mPCIe WiFi
- mPCIe Bluetooth (uses USB)

Not working:
- Brightness hotkeys
- Physical Wireless switch
- SD card slot: Linux outputs an "irq 18: nobody cared" message when
  inserting a card, after which it disables the IRQ

Unknown/untested:
- Dock
- Smartcard (slot and contactless)
- Firewire
- eSATA
- TPM
- Battery (my battery is at the end of its lifespan)

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I516ebbf4390a3f6d242050da8d35dc267b8b3a28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

20 files changed, 605 insertions, 0 deletions

diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
new file mode 100644
index 0000000000..034de4be2b
--- /dev/null
+++ b/src/mainboard/dell/e6400/Kconfig
@@ -0,0 +1,32 @@
+if BOARD_DELL_E6400
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SYSTEM_TYPE_LAPTOP
+	select CPU_INTEL_SOCKET_P
+	select NORTHBRIDGE_INTEL_GM45
+	select SOUTHBRIDGE_INTEL_I82801IX
+	select BOARD_ROMSIZE_KB_4096
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select HAVE_ACPI_RESUME
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select INTEL_GMA_HAVE_VBT
+	select EC_DELL_MEC5035
+
+config MAINBOARD_DIR
+	default "dell/e6400"
+
+config MAINBOARD_PART_NUMBER
+	default "Latitude E6400" if BOARD_DELL_E6400
+
+config USBDEBUG_HCD_INDEX
+	default 1
+
+config CBFS_SIZE
+	default 0x1A0000
+
+endif # BOARD_DELL_E6400
diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/e6400/Kconfig.name
new file mode 100644
index 0000000000..c500f96f5f
--- /dev/null
+++ b/src/mainboard/dell/e6400/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_E6400
+	bool "Latitude E6400"
diff --git a/src/mainboard/dell/e6400/Makefile.inc b/src/mainboard/dell/e6400/Makefile.inc
new file mode 100644
index 0000000000..ca3a82db48
--- /dev/null
+++ b/src/mainboard/dell/e6400/Makefile.inc
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += gpio.c
+
+ramstage-y += cstates.c
+ramstage-y += blc.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/e6400/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/dell/e6400/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
new file mode 100644
index 0000000000..21066fbf3b
--- /dev/null
+++ b/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH9
+ */
+
+/* TODO: which slots are actually relevant? */
+If (PICM) {
+	Return (Package() {
+		// PCI Slot 1 routes ABCD
+		Package() { 0x0000ffff, 0, 0, 16},
+		Package() { 0x0000ffff, 1, 0, 17},
+		Package() { 0x0000ffff, 2, 0, 18},
+		Package() { 0x0000ffff, 3, 0, 19},
+
+		// PCI Slot 2 routes BCDA
+		Package() { 0x0001ffff, 0, 0, 17},
+		Package() { 0x0001ffff, 1, 0, 18},
+		Package() { 0x0001ffff, 2, 0, 19},
+		Package() { 0x0001ffff, 3, 0, 16},
+
+		// PCI Slot 3 routes CDAB
+		Package() { 0x0002ffff, 0, 0, 18},
+		Package() { 0x0002ffff, 1, 0, 19},
+		Package() { 0x0002ffff, 2, 0, 16},
+		Package() { 0x0002ffff, 3, 0, 17},
+
+		// PCI Slot 4 routes ABCD
+		Package() { 0x0003ffff, 0, 0, 16},
+		Package() { 0x0003ffff, 1, 0, 17},
+		Package() { 0x0003ffff, 2, 0, 18},
+		Package() { 0x0003ffff, 3, 0, 19},
+
+		// PCI Slot 5 routes ABCD
+		Package() { 0x0004ffff, 0, 0, 16},
+		Package() { 0x0004ffff, 1, 0, 17},
+		Package() { 0x0004ffff, 2, 0, 18},
+		Package() { 0x0004ffff, 3, 0, 19},
+
+		// PCI Slot 6 routes BCDA
+		Package() { 0x0005ffff, 0, 0, 17},
+		Package() { 0x0005ffff, 1, 0, 18},
+		Package() { 0x0005ffff, 2, 0, 19},
+		Package() { 0x0005ffff, 3, 0, 16},
+
+		// FIXME: what's this supposed to mean? (adopted from ich7)
+		//Package() { 0x0008ffff, 0, 0, 20},
+	})
+} Else {
+	Return (Package() {
+		// PCI Slot 1 routes ABCD
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		// PCI Slot 2 routes BCDA
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		// PCI Slot 3 routes CDAB
+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
+
+		// PCI Slot 4 routes ABCD
+		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		// PCI Slot 5 routes ABCD
+		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		// PCI Slot 6 routes BCDA
+		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		// FIXME
+		// Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+	})
+}
diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/e6400/acpi/superio.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/dell/e6400/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/e6400/blc.c
new file mode 100644
index 0000000000..b01d552850
--- /dev/null
+++ b/src/mainboard/dell/e6400/blc.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <northbridge/intel/gm45/gm45.h>
+
+/*
+ * This contains a list of panel IDs and a known well working
+ * backlight PWM frequency.
+ */
+static const struct blc_pwm_t blc_entries[] = {
+	/*
+	 * Not sure if that's just a corrupt byte or just something
+	 * weird about the EDID of the panel in my system. Also, the
+	 * vendor firmware sets the pwm frequency to a rather high
+	 * value compared to other GM45 systems in the tree.
+	 */
+	{"G022H\200141WX5", 12315},
+};
+
+int get_blc_values(const struct blc_pwm_t **entries)
+{
+	*entries = blc_entries;
+	return ARRAY_SIZE(blc_entries);
+}
diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/e6400/board_info.txt
new file mode 100644
index 0000000000..91a6188f0b
--- /dev/null
+++ b/src/mainboard/dell/e6400/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2008
diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/e6400/bootblock.c
new file mode 100644
index 0000000000..c72622e7d7
--- /dev/null
+++ b/src/mainboard/dell/e6400/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
new file mode 100644
index 0000000000..eeb6f47364
--- /dev/null
+++ b/src/mainboard/dell/e6400/cmos.default
@@ -0,0 +1,5 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=32M
diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/e6400/cmos.layout
new file mode 100644
index 0000000000..e32207ac6b
--- /dev/null
+++ b/src/mainboard/dell/e6400/cmos.layout
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+
+#400	8	r	0	reserved for century byte
+
+# coreboot config options: southbridge
+408	1	e	10	sata_mode
+409	2	e	7	power_on_after_fail
+
+# coreboot config options: bootloader
+432	512	s	0	boot_devices
+944	8	h	0	boot_default
+
+# coreboot config options: northbridge
+954	4	e	11	gfx_uma_size
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# RAM initialization internal data
+1024	128	r	0	read_training_results
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+10	0	AHCI
+10	1	Compatible
+11	4	32M
+11	5	48M
+11	6	64M
+11	7	128M
+11	8	256M
+11	9	96M
+11	10	160M
+11	11	224M
+11	12	352M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/e6400/cstates.c
new file mode 100644
index 0000000000..b435d83c01
--- /dev/null
+++ b/src/mainboard/dell/e6400/cstates.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+
+static const acpi_cstate_t cst_entries[] = {
+	{
+		/* ACPI C1 / CPU C1 */
+		1, 0x01, 1000,
+		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0, 0 }
+	},
+	{
+		/* ACPI C2 / CPU C2 */
+		2, 0x01,  500,
+		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0x10, 0 }
+	},
+	{
+		/* acpi C3 / cpu C3 */
+		3, 0x37,  250,
+		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0x20, 0 }
+	},
+};
+
+int get_cst_entries(const acpi_cstate_t **entries)
+{
+	*entries = cst_entries;
+	return ARRAY_SIZE(cst_entries);
+}
diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/e6400/data.vbt
new file mode 100644
index 0000000000..d5f37e787d
--- /dev/null
+++ b/src/mainboard/dell/e6400/data.vbt
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
new file mode 100644
index 0000000000..bb954cbd7b
--- /dev/null
+++ b/src/mainboard/dell/e6400/devicetree.cb
@@ -0,0 +1,98 @@
+chip northbridge/intel/gm45
+	# IGD Displays
+	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+
+	register "gpu_panel_power_up_delay" = "250"		# T1+T2: 25ms
+	register "gpu_panel_power_down_delay" = "250"		# T3:    25ms
+	register "gpu_panel_power_backlight_on_delay" = "2500"	# T5:   250ms
+	register "gpu_panel_power_backlight_off_delay" = "2500"	# Tx:   250ms
+	register "gpu_panel_power_cycle_delay" = "3"		# T4:   200ms
+
+	register "slfm" = "1"
+
+	device cpu_cluster 0 on ops gm45_cpu_bus_ops end
+
+	register "pci_mmio_size" = "2048"
+
+	device domain 0 on
+		subsystemid 0x1028 0x0233 inherit
+		ops gm45_pci_domain_ops
+
+		device pci 00.0 on end # host bridge
+		device pci 01.0 off end
+		device pci 02.0 on end # VGA
+		device pci 02.1 on end # Display
+		device pci 03.0 on end # ME
+		device pci 03.1 off end # ME
+		device pci 03.2 off end # ME
+		device pci 03.3 off end # ME
+		chip southbridge/intel/i82801ix
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x03"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0a"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x80"
+
+			register "gpi8_routing"  = "2"
+			register "gpe0_en" = "0x01000000"
+			register "gpi1_routing"  = "2"
+
+			# Set AHCI mode, enable ports 1 and 2.
+			register "sata_port_map"		= "0x03"
+			register "sata_clock_request"		= "0"
+			register "sata_traffic_monitor"		= "0"
+
+			# Set c-state support
+			register "c4onc3_enable"		= "1"
+			register "c5_enable"			= "1"
+			register "c6_enable"			= "1"
+
+			# Set thermal throttling to 75%.
+			register "throttle_duty"		= "THTL_75_0"
+
+			# Enable PCIe ports 1,2,4 as slots (Mini * PCIe).
+			register "pcie_slot_implemented"	= "0xb"
+			# Set power limits to 10 * 10^0 watts.
+			# Maybe we should set less for Mini PCIe.
+			register "pcie_power_limits" = "{
+				[0] = { 10, 0 },
+				[1] = { 10, 0 },
+				[3] = { 10, 0 },
+			}"
+			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+			register "gen1_dec" = "0x007c0901"
+
+			device pci 19.0 on end # LAN
+			device pci 1a.0 on end # UHCI
+			device pci 1a.1 on end # UHCI
+			device pci 1a.2 on end # UHCI
+			device pci 1a.7 on end # EHCI
+			device pci 1b.0 on end # HD Audio
+			device pci 1c.0 on end # PCIe Port #1 (WWAN)
+			device pci 1c.1 on end # PCIe Port #2 (WLAN)
+			device pci 1c.2 on end # PCIe Port #3 (UWB)
+			device pci 1c.3 on # Expresscard
+				smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
+			end # PCIe Port #4
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1d.0 on end # UHCI
+			device pci 1d.1 on end # UHCI
+			device pci 1d.2 on end # UHCI
+			device pci 1d.7 on end # EHCI
+			device pci 1e.0 on end # PCI
+			device pci 1f.0 on # LPC bridge
+				chip ec/dell/mec5035
+					device pnp ff.0 on end
+                                end
+			end
+			device pci 1f.2 on end # SATA/IDE 1
+			device pci 1f.3 on end	# SMBus
+			device pci 1f.5 off end # SATA/IDE 2
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/e6400/dsdt.asl
new file mode 100644
index 0000000000..73bc07481c
--- /dev/null
+++ b/src/mainboard/dell/e6400/dsdt.asl
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20090419	// OEM revision
+)
+{
+	#include <acpi/dsdt_top.asl>
+
+	#include <southbridge/intel/i82801ix/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+
+	#include <cpu/intel/speedstep/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0) {
+			#include <northbridge/intel/gm45/acpi/gm45.asl>
+			#include <southbridge/intel/i82801ix/acpi/ich9.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		}
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+}
diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/e6400/gma-mainboard.ads
new file mode 100644
index 0000000000..a6b1397058
--- /dev/null
+++ b/src/mainboard/dell/e6400/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1, -- mainboard DP
+      DP2, -- dock DP
+      Analog, -- mainboard VGA
+      LVDS,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/e6400/gpio.c
new file mode 100644
index 0000000000..a6d3d74abe
--- /dev/null
+++ b/src/mainboard/dell/e6400/gpio.c
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_GPIO,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_GPIO,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio9 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_OUTPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio20 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_GPIO,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio60 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio56 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio39 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode = &pch_gpio_set1_mode,
+		.direction = &pch_gpio_set1_direction,
+		.level = &pch_gpio_set1_level,
+		.blink = &pch_gpio_set1_blink,
+		.invert = &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode = &pch_gpio_set2_mode,
+		.direction = &pch_gpio_set2_direction,
+		.level = &pch_gpio_set2_level,
+	},
+};
diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/e6400/hda_verb.c
new file mode 100644
index 0000000000..2b4c37e2e2
--- /dev/null
+++ b/src/mainboard/dell/e6400/hda_verb.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x111d76b2, /* IDT 92HD71B7X */
+	0x10280233, /* Subsystem ID */
+	13,	    /* Number of entries */
+
+	/* Pin Widget Verb Table */
+
+	AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
+	AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
+	AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
+	AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
+	AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
+	AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
+	AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
+	AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
+};
+
+const u32 pc_beep_verbs[] = {
+	0x00170500, /* power up codec */
+	0x00d70500, /* power up speakers */
+	0x00d70102, /* select mixer (input 0x2) for speakers */
+	0x00d70740, /* enable speakers output */
+	0x02770720, /* enable beep input */
+	0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
+	0x00d37000, /* unmute speakers */
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/e6400/mainboard.c
new file mode 100644
index 0000000000..f9858e6d00
--- /dev/null
+++ b/src/mainboard/dell/e6400/mainboard.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+					GMA_INT15_PANEL_FIT_CENTERING,
+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 2);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/e6400/romstage.c
new file mode 100644
index 0000000000..dabef34707
--- /dev/null
+++ b/src/mainboard/dell/e6400/romstage.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <northbridge/intel/gm45/gm45.h>
+
+void get_mb_spd_addrmap(u8 spd_addrmap[4])
+{
+	spd_addrmap[0] = 0x50;
+	spd_addrmap[2] = 0x52;
+}