diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-06-25 21:55:35 +0530 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-06-26 00:15:04 +0000 |
| commit | 469dda33397cb2bf971931fd3c06ed9b46a62a4c (patch) | |
| tree | 2be078da1b0e0811879384777e44e8919f41bb49 | |
| parent | 154625bcb2cac1f120a9d0c03da00f2e8c524273 (diff) | |
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, Reset Power Cycle Duration is set with default value (4s).
This adds around ~5 seconds of delay during power cycle or global reset.
So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s
to minimize the delay.
Delay with Power Cycle or Global Reset:
Existing behaviour:
S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch:
S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert.
The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width
to 98ms not 2s.
Test=Verified on Hatch and Puff boards
BUG=b:158634281
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2d3156ae6b..cb314ab6a2 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -142,7 +142,15 @@ chip soc/intel/cannonlake register "PchPmSlpS3MinAssert" = "2" # 50ms register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "1" # 500ms - register "PchPmSlpAMinAssert" = "3" # 2s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s # Enable Audio DSP oscillator qualification for S0ix register "cppmvric2_adsposcdis" = "1" |