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authorSubrata Banik <subrata.banik@intel.com>2020-11-22 15:16:12 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-11-23 03:37:33 +0000
commit447233ce8c25863c2236d0b208bff7f63cd738fb (patch)
tree4a4e261d4a039c97145b26ae78e31b9085e3397c
parent8ed53ec8c06c7468a3c4ea1e8fb40012cc375d38 (diff)
soc/intel/alderlake: Update UART0 GPIO as per latest schematics
UART0_RX: C8 -> H10 UART0_TX: C9 -> H11 GPIO PIN Mode: NF1 -> NF2 Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/soc/intel/alderlake/uart.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c
index cdbf8ec123..a3bdc4a3ba 100644
--- a/src/soc/intel/alderlake/uart.c
+++ b/src/soc/intel/alderlake/uart.c
@@ -21,8 +21,8 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
{
.console_index = 0,
.gpios = {
- PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
- PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */
},
},
{