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authorMalik_Hsu <malik_hsu@wistron.corp-partner.google.com>2021-11-11 10:15:28 +0800
committerWerner Zeh <werner.zeh@siemens.com>2021-11-15 10:03:06 +0000
commit434fa6367f140f7a9161c759904a3d193dbe62a7 (patch)
treee6dea39aaffb8bd8058b13998071210dee5a1897
parent07e6b5f67d4b5e957a56d6dbcd7328238f1074fe (diff)
mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less than 1, do not enable RTD3 driver. BUG=b:204469567 TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
-rw-r--r--src/mainboard/google/brya/variants/primus/Makefile.inc1
-rw-r--r--src/mainboard/google/brya/variants/primus/gpio.c4
-rw-r--r--src/mainboard/google/brya/variants/primus/overridetree.cb5
-rw-r--r--src/mainboard/google/brya/variants/primus/variant.c20
4 files changed, 28 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/primus/Makefile.inc b/src/mainboard/google/brya/variants/primus/Makefile.inc
index 129a2938e3..725b883fba 100644
--- a/src/mainboard/google/brya/variants/primus/Makefile.inc
+++ b/src/mainboard/google/brya/variants/primus/Makefile.inc
@@ -3,3 +3,4 @@ bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c
index c1dfee2f6c..a324fa3454 100644
--- a/src/mainboard/google/brya/variants/primus/gpio.c
+++ b/src/mainboard/google/brya/variants/primus/gpio.c
@@ -45,8 +45,6 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E3, NONE),
/* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE),
- /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
- PAD_CFG_GPO(GPP_E20, 1, DEEP),
/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
@@ -107,6 +105,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_E16, 0, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+ /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
+ PAD_CFG_GPO(GPP_E20, 1, DEEP),
/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
PAD_CFG_GPO(GPP_F21, 0, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index 81dc1c03aa..8028798f3c 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -128,6 +128,11 @@ chip soc/intel/alderlake
end
end
device ref pcie_rp3 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
+ register "srcclk_pin" = "6"
+ device generic 0 alias emmc_rtd3 on end
+ end
# Enable PCIe-to-eMMC bridge PCIE 3 using clk 6
register "pch_pcie_rp[PCH_RP(3)]" = "{
.clk_src = 6,
diff --git a/src/mainboard/google/brya/variants/primus/variant.c b/src/mainboard/google/brya/variants/primus/variant.c
new file mode 100644
index 0000000000..4780334779
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus/variant.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <device/device.h>
+
+static void devtree_update_emmc_rtd3(uint32_t board_ver)
+{
+ struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3);
+ if (board_ver > 1)
+ return;
+
+ emmc_rtd3->enabled = 0;
+}
+
+void variant_devtree_update(void)
+{
+ uint32_t board_ver = board_id();
+ devtree_update_emmc_rtd3(board_ver);
+}