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authorShon Wang <shon.wang@quanta.corp-partner.google.com>2023-06-19 13:30:32 +0800
committerFelix Held <felix-coreboot@felixheld.de>2023-06-26 15:33:08 +0000
commit4326128fd3bab20782b45fa1fb8e63592d5142db (patch)
tree2f861a0ea79b4fc7c0bdb70f7b2afb8b67ee903f
parent249aede238050e6a6ab71d3c6fb72aa5b5d4e78f (diff)
mb/google/brya/var/vell: update FW_config to sync config.star
We have found inconsistencies in turn of FW_CONFIG settings/definitions, so sync setting to vell config.star BUG=b:282189358 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I676b719ecc711a6f59e76465a3566bf63924d90f Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75913 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/brya/variants/vell/overridetree.cb44
1 files changed, 16 insertions, 28 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 1100628309..5298a7e358 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -1,24 +1,19 @@
fw_config
- field DB_SD 0 1
- option SD_ABSENT 0
- option SD_GL9750 1
+ field DB_CELLULAR 0 0
+ option DB_CELLULAR_ABSENT 0
+ option DB_CELLULAR_PCIE 1
end
- field KB_BL 2 2
- option KB_BL_ABSENT 0
- option KB_BL_PRESENT 1
+ field KB_COLOR 1 1
+ option KB_COLOR_WHITE 0
+ option KB_COLOR_BLUE 1
end
- field AUDIO 3 5
- option AUDIO_UNKNOWN 0
- option MAX98360_ALC5682I_I2S 1
- option MAX98360_ALC5682IVS_I2S 2
+ field NAND 2 2
+ option NAND_MICRON 0
+ option NAND_KIOXIA 1
end
- field DB_LTE 6 7
- option LTE_ABSENT 0
- option LTE_USB 1
- end
- field EPS 10 10
- option PRIVACY_SCREEN_ABSENT 0
- option PRIVACY_SCREEN 1
+ field WIFI_SAR_ID 30 31
+ option WIFI_SAR_ID_0 0
+ option WIFI_SAR_ID_1 1
end
end
chip soc/intel/alderlake
@@ -97,18 +92,11 @@ chip soc/intel/alderlake
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "1"
+ # DDIA for eDP
register "device[0].name" = ""LCD""
- # Use ChromeOS privacy screen _HID
- register "device[0].hid" = ""GOOG0010""
- # Internal panel on the first port of the graphics chip
- register "device[0].addr" = "0x80010400"
- register "device[0].privacy.enabled" = "1"
- register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H21)"
- device generic 0 on
- probe EPS PRIVACY_SCREEN
- end
- end
- end # Integrated Graphics Device
+ device generic 0 on end
+ end
+ end # Integrated Graphics Device
device ref dtt on
chip drivers/intel/dptf
## sensor information