diff options
| author | Patrick Georgi <pgeorgi@chromium.org> | 2016-02-08 20:28:32 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-02-09 21:53:22 +0100 |
| commit | 42636a7a0cfeff36988fad97337a9d88e4f0e7b2 (patch) | |
| tree | eb49dbb8c1bd17198318a39a8aab6ae25cc7eb30 | |
| parent | 15f4d8c1bb79ff1d0c545b4ed5f498177f585b83 (diff) | |
rockchip/rk3288: UART uses 32bit wide registers
Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13635
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/soc/rockchip/rk3288/uart.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c index 98477344d3..8576dc18e3 100644 --- a/src/soc/rockchip/rk3288/uart.c +++ b/src/soc/rockchip/rk3288/uart.c @@ -155,7 +155,7 @@ void uart_fill_lb(void *data) serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; serial.baud = default_baudrate(); - serial.regwidth = 1; + serial.regwidth = 4; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); |