tegra132: refactor cpu startup code

In order to more easily bring up the 2nd core refactor
the cpu startup logic. A common 32bit_entry.S is compiled
both for romstage and ramstage to provide the common 32-bit
entry point.

BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted ryu to the kernel. Also, can get the 2nd
     core up out of reset.

Change-Id: I0c2c9f637189009767e8d5510732678c64e62a2a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7394b271bf67dfad8a601f41faaac8f07ae6d4a5
Original-Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213850
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9001
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

6 files changed, 170 insertions, 60 deletions

diff --git a/src/soc/nvidia/tegra132/32bit_reset.S b/src/soc/nvidia/tegra132/32bit_reset.S
new file mode 100644
index 0000000000..ce92dc50de
--- /dev/null
+++ b/src/soc/nvidia/tegra132/32bit_reset.S
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * This code is compiled for both arm64 and arm4, however the code is only
+ * executed by the armv8 cores coming out of reset.
+ */
+
+#if !defined(__PRE_RAM__)
+#define INST .inst
+#else
+#define INST .word
+#endif
+
+/*
+ * The Denver cores come up in aarch32 mode. In order to transition to
+ * 64-bit mode a write to the RMR (reest mangement register) with the
+ * AA64 bit (0) set while setting RR (reset request bit 1).
+ */
+.align 6
+.global reset_entry_32bit
+reset_entry_32bit:
+	INST	0xe3a00003	/* mov r0, #3 */
+	INST	0xee0c0f50	/* mcr 15, 0, r0, cr12, cr0, {2} */
+	INST	0xeafffffe	/* b . */
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index b489d52afb..96961c8027 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -20,6 +20,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
 bootblock-$(CONFIG_DRIVERS_UART) += uart.c
 endif
 
+romstage-y += 32bit_reset.S
 romstage-y += romstage_asm.S
 romstage-y += addressmap.c
 romstage-y += cbfs.c
@@ -27,6 +28,7 @@ romstage-y += cbmem.c
 romstage-y += timer.c
 romstage-y += ccplex.c
 romstage-y += clock.c
+romstage-y += cpu.c
 romstage-y += reset.c
 romstage-y += spi.c
 romstage-y += i2c.c
@@ -45,9 +47,11 @@ romstage-y += ../tegra/pinmux.c
 romstage-y += ../tegra/usb.c
 romstage-$(CONFIG_DRIVERS_UART) += uart.c
 
+ramstage-y += 32bit_reset.S
 ramstage-y += addressmap.c
 ramstage-y += cbfs.c
 ramstage-y += cbmem.c
+ramstage-y += cpu.c
 ramstage-y += timer.c
 ramstage-y += clock.c
 ramstage-y += soc.c
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index 90818b5515..1085b285ad 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -23,6 +23,7 @@
 #include <cbfs.h>
 #include <timer.h>
 #include <soc/addressmap.h>
+#include <soc/cpu.h>
 #include <soc/romstage.h>
 #include "clk_rst.h"
 #include "ccplex.h"
@@ -31,7 +32,6 @@
 #include "pmc.h"
 #include "power.h"
 
-#define EVP_CPU_RESET_VECTOR (void *)(uintptr_t)(TEGRA_EVP_BASE + 0x100)
 #define CLK_RST_REGS (void *)(uintptr_t)(TEGRA_CLK_RST_BASE)
 #define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE)
 #define MTS_FILE_NAME "mts"
@@ -130,7 +130,6 @@ static void enable_cpu_power_partitions(void)
 	power_ungate_partition(POWER_PARTID_CE1);
 }
 
-
 static void request_ram_repair(void)
 {
 	struct flow_ctlr * const flow = (void *)(uintptr_t)TEGRA_FLOW_BASE;
@@ -164,73 +163,22 @@ void ccplex_cpu_prepare(void)
 	request_ram_repair();
 }
 
-static void start_cpu0(void)
+static void start_common_clocks(void)
 {
 	struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS;
 
 	/* Clear fast CPU partition reset. */
 	write32(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr);
 
-	/* Clear reset of CPU0 components. */
-	write32(CRC_RST_CPUG_CLR_CPU0 |
-		CRC_RST_CPUG_CLR_DBG0 |
-		CRC_RST_CPUG_CLR_CORE0 |
-		CRC_RST_CPUG_CLR_CX0 |
-		CRC_RST_CPUG_CLR_L2 |
-		CRC_RST_CPUG_CLR_PDBG, &clk_rst->rst_cpug_cmplx_clr);
-}
-
-/*
- * The Denver cores come up in aarch32 mode. In order to transition to
- * 64-bit mode a write to the RMR (reset mangement register) with the
- * AA64 bit (0) set while setting RR (reset request bit 1).
- */
-static const uint32_t aarch32to64[] = {
-	0xe3a00003,       /* mov     r0, #3 */
-	0xee0c0f50,       /* mcr     15, 0, r0, cr12, cr0, {2} */
-};
-
-static void load_aarch64_trampoline(void *addr)
-{
-	const size_t trampoline_size = sizeof(aarch32to64);
-	const void * const trampoline = &aarch32to64[0];
-
-	/* Copy trampoline into ram. */
-	memcpy(addr, trampoline, trampoline_size);
+	/* Clear reset of L2 and CoreSight components. */
+	write32(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
+		&clk_rst->rst_cpug_cmplx_clr);
 }
 
 void ccplex_cpu_start(void *entry_addr)
 {
-	struct tegra_pmc_regs * const pmc = PMC_REGS;
-	void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR;
-	void *trampoline;
-	uint32_t entry_point;
-
-	/*
-	 * Just place the trampoline at the MTS_LOAD_ADDRESS. This assumes
-	 * the program to run doesn't overlap this address.
-	 */
-	const uint32_t trampoline_addr = MTS_LOAD_ADDRESS;
-	trampoline = (void *)(uintptr_t)trampoline_addr;
-
-	/* The arm entry points have bit 0 set if thumb code. Mask that off. */
-	entry_point = (uint32_t)(uintptr_t)entry_addr;
-
-	load_aarch64_trampoline(trampoline);
-
-	/* Warm reset vector is pulled from the PMC scratch registers. */
-	write32(entry_point, &pmc->secure_scratch34);
-	write32(0, &pmc->secure_scratch35);
-
-	printk(BIOS_DEBUG, "Starting CPU0 @ %p trampolining to %08x.\n",
-		trampoline, entry_point);
-
-	/*
-	 * The Denver cores start in 32-bit mode. Therefore a trampoline
-	 * is needed to get into 64-bit mode. Point the cold reset vector
-	 * to the trampoline location.
-	 */
-	write32(trampoline_addr, evp_cpu_reset_vector);
+	/* Enable common clocks for the shared resources between the cores. */
+	start_common_clocks();
 
-	start_cpu0();
+	start_cpu(0, entry_addr);
 }
diff --git a/src/soc/nvidia/tegra132/ccplex.h b/src/soc/nvidia/tegra132/ccplex.h
index c3f8a04534..bd0679b259 100644
--- a/src/soc/nvidia/tegra132/ccplex.h
+++ b/src/soc/nvidia/tegra132/ccplex.h
@@ -20,6 +20,8 @@
 #ifndef __SOC_NVIDIA_TEGRA132_CCPLEX_H__
 #define __SOC_NVIDIA_TEGRA132_CCPLEX_H__
 
+#include <stdint.h>
+
 #define MTS_LOAD_ADDRESS 0x82000000
 
 /* Prepare the clocks and rails to start the cpu. */
diff --git a/src/soc/nvidia/tegra132/cpu.c b/src/soc/nvidia/tegra132/cpu.c
new file mode 100644
index 0000000000..04704518ba
--- /dev/null
+++ b/src/soc/nvidia/tegra132/cpu.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <soc/addressmap.h>
+#include <soc/cpu.h>
+#include "clk_rst.h"
+#include "pmc.h"
+
+#define EVP_CPU_RESET_VECTOR (void *)(uintptr_t)(TEGRA_EVP_BASE + 0x100)
+#define CLK_RST_REGS (void *)(uintptr_t)(TEGRA_CLK_RST_BASE)
+#define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE)
+
+static void enable_core_clocks(int cpu)
+{
+	struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS;
+
+	const uint32_t cpu0_clocks = CRC_RST_CPUG_CLR_CPU0 |
+					CRC_RST_CPUG_CLR_DBG0 |
+					CRC_RST_CPUG_CLR_CORE0 |
+					CRC_RST_CPUG_CLR_CX0;
+	const uint32_t cpu1_clocks = CRC_RST_CPUG_CLR_CPU1 |
+					CRC_RST_CPUG_CLR_DBG1 |
+					CRC_RST_CPUG_CLR_CORE1 |
+					CRC_RST_CPUG_CLR_CX1;
+
+	/* Clear reset of CPU components. */
+	if (cpu == 0)
+		write32(cpu0_clocks, &clk_rst->rst_cpug_cmplx_clr);
+	else
+		write32(cpu1_clocks, &clk_rst->rst_cpug_cmplx_clr);
+}
+
+static void set_armv8_32bit_reset_vector(uintptr_t entry)
+{
+	void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR;
+	write32(entry, evp_cpu_reset_vector);
+}
+
+static void set_armv8_64bit_reset_vector(uintptr_t entry)
+{
+	struct tegra_pmc_regs * const pmc = PMC_REGS;
+
+	/* Currently assume 32-bit addresses only. */
+	write32(entry, &pmc->secure_scratch34);
+	write32(0, &pmc->secure_scratch35);
+}
+
+
+void start_cpu(int cpu, void *entry_64)
+{
+	printk(BIOS_DEBUG, "Starting CPU%d @ %p trampolining to %p.\n",
+		cpu, reset_entry_32bit, entry_64);
+
+	/* Warm reset vector is pulled from the PMC scratch registers. */
+	set_armv8_64bit_reset_vector((uintptr_t)entry_64);
+
+	/*
+	 * The Denver cores start in 32-bit mode. Therefore a trampoline
+	 * is needed to get into 64-bit mode. Point the cold reset vector
+	 * to the traompoline location.
+	 */
+	set_armv8_32bit_reset_vector((uintptr_t)reset_entry_32bit);
+
+	enable_core_clocks(cpu);
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/cpu.h b/src/soc/nvidia/tegra132/include/soc/cpu.h
new file mode 100644
index 0000000000..c957d59608
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/cpu.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_CPU_H__
+#define __SOC_NVIDIA_TEGRA132_CPU_H__
+
+/*
+ * Start a core in 64-bit mode at the entry_64 address. Note that entry_64
+ * should be a 32-bit address.
+ */
+void start_cpu(int cpu, void *entry_64);
+
+void reset_entry_32bit(void);
+
+#endif /* __SOC_NVIDIA_TEGRA132_CPU_H__ */
+