soc/cavium: Enable DRAM test

Enable fast or extended DRAM test based on devicetree setting.
The fast DRAM test takes less than a second, while the
extended runs about 1 minute.

Tested on Cavium Soc.

Change-Id: I6a375f3d4c5cea7c3c0cd4592287f3f85dc7d3cf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

2 files changed, 26 insertions, 17 deletions

diff --git a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c
index 8775886263..237e73d917 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c
+++ b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c
@@ -20,6 +20,7 @@
 #include <bdk-devicetree.h>
 
 const struct bdk_devicetree_key_value devtree[] = {
+{"DDR-TEST-BOOT", "1"},
 {"DDR-CONFIG-DQX-CTL", "0x4"},
 {"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"},
 {"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"},
diff --git a/src/soc/cavium/cn81xx/sdram.c b/src/soc/cavium/cn81xx/sdram.c
index 77717ea78d..2342b049ef 100644
--- a/src/soc/cavium/cn81xx/sdram.c
+++ b/src/soc/cavium/cn81xx/sdram.c
@@ -58,30 +58,38 @@ void sdram_init(void)
 
 	/* See if we should test this node's DRAM during boot */
 	int test_dram = bdk_config_get_int(BDK_CONFIG_DRAM_BOOT_TEST, 0);
-	if (test_dram) {
+	if (test_dram == 1) {
+		static const u8 tests[] = {13, 0, 1};
+		for (size_t i = 0; i < ARRAY_SIZE(tests); i++) {
+			/* Run the address test to make sure DRAM works */
+			if (bdk_dram_test(tests[i], 4 * MiB,
+					  sdram_size_mb() * MiB - 4 * MiB,
+					  BDK_DRAM_TEST_NO_STATS |
+					  BDK_DRAM_TEST_NODE0)) {
+				printk(BIOS_CRIT, "%s: Failed DRAM test.\n",
+				       __func__);
+			}
+			bdk_watchdog_poke();
+		}
+	} else {
 		/* Run the address test to make sure DRAM works */
-		if (bdk_dram_test(13, 0, 0x10000000000ull, BDK_DRAM_TEST_NO_STATS | (1<<0))) {
+		if (bdk_dram_test(13, 4 * MiB,
+			  sdram_size_mb() * MiB - 4 * MiB,
+			  BDK_DRAM_TEST_NO_STATS |
+			  BDK_DRAM_TEST_NODE0)) {
 			/**
-			 * FIXME(dhendrix): This should be handled by mainboard code since we
-			 * don't necessarily have a BMC to report to. Also, we need to figure out
-			 * if we need to keep going as to avoid getting into a boot loop.
+			 * FIXME(dhendrix): This should be handled by mainboard
+			 * code since we don't necessarily have a BMC to report
+			 * to. Also, we need to figure out if we need to keep
+			 * going as to avoid getting into a boot loop.
 			 */
 			// bdk_boot_status(BDK_BOOT_STATUS_REQUEST_POWER_CYCLE);
-			printk(BIOS_ERR, "%s: Failed DRAM test.\n", __func__);
+			printk(BIOS_CRIT, "%s: Failed DRAM test.\n", __func__);
 		}
-		bdk_watchdog_poke();
-		/* Put other node core back in reset */
-		if (0 != bdk_numa_master())
-			BDK_CSR_WRITE(0, BDK_RST_PP_RESET, -1);
-		/* Clear DRAM */
-		uint64_t skip = 0;
-		if (0 == bdk_numa_master())
-			skip = bdk_dram_get_top_of_bdk();
-		void *base = bdk_phys_to_ptr(bdk_numa_get_address(0, skip));
-		bdk_zero_memory(base, ((uint64_t)mbytes << 20) - skip);
-		bdk_watchdog_poke();
 	}
 
+	bdk_watchdog_poke();
+
 	/* Unlock L2 now that DRAM works */
 	if (0 == bdk_numa_master()) {
 		uint64_t l2_size = bdk_l2c_get_cache_size_bytes(0);