diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-16 14:58:34 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:36:04 +0000 |
| commit | 3ef8e21f3313b2e15b2fd09fc180a0a0a355a1df (patch) | |
| tree | 296e08fdcd5ca5775a5f9736a49c9da0daaa9d17 | |
| parent | 26e880e8a3ed87bbc918692e929fa7e1560cb3e3 (diff) | |
soc/intel/broadwell/bootblock.c: Remove repeated word
Change-Id: I3aec07d782e4315120a4365a65bdbcbf4a22e6f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
| -rw-r--r-- | src/soc/intel/broadwell/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c index 5edfaeecaf..1e32f357a1 100644 --- a/src/soc/intel/broadwell/bootblock.c +++ b/src/soc/intel/broadwell/bootblock.c @@ -12,7 +12,7 @@ void bootblock_early_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to - * to true. That way all subsequent non-explicit config accesses use + * true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the |