diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2020-12-23 04:29:57 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-25 09:11:03 +0000 |
| commit | 3ec3cb82f9ad5d71d19bc461177cca19f9ec6a59 (patch) | |
| tree | 09cc2e0fce5be214a614476514afe086c2f47687 | |
| parent | 27b149c30be25359500f167cddde143e7291da93 (diff) | |
soc/amd/picasso: Add UPDs for support eDP power sequence adjust
Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.
BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 14 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fsp_params.c | 11 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 94983038ac..be30efa87c 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -243,6 +243,20 @@ struct soc_amd_picasso_config { uint8_t boostadj; uint16_t margin_deemph; } edp_tuningset; + + /* + * eDP panel power sequence control + * all pwr sequence numbers below are in uint of 4ms and "0" as default value + */ + uint8_t edp_pwr_adjust_enable; + uint8_t pwron_digon_to_de; + uint8_t pwron_de_to_varybl; + uint8_t pwrdown_varybloff_to_de; + uint8_t pwrdown_de_to_digoff; + uint8_t pwroff_delay; + uint8_t pwron_varybl_to_blon; + uint8_t pwrdown_bloff_to_varybloff; + uint8_t min_allowed_bl_level; }; #endif /* __PICASSO_CHIP_H__ */ diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 3a27a16172..731a564416 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -152,6 +152,17 @@ static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg, scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4; scfg->BoostAdj = cfg->edp_tuningset.boostadj; } + if (cfg->edp_pwr_adjust_enable) { + scfg->pwron_digon_to_de = cfg->pwron_digon_to_de; + scfg->pwron_de_to_varybl = cfg->pwron_de_to_varybl; + scfg->pwrdown_varybloff_to_de = cfg->pwrdown_varybloff_to_de; + scfg->pwrdown_de_to_digoff = cfg->pwrdown_de_to_digoff; + scfg->pwroff_delay = cfg->pwroff_delay; + scfg->pwron_varybl_to_blon = cfg->pwron_varybl_to_blon; + scfg->pwrdown_bloff_to_varybloff = cfg->pwrdown_bloff_to_varybloff; + scfg->min_allowed_bl_level = cfg->min_allowed_bl_level; + } + } void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |