diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2022-01-27 09:23:22 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-03 13:49:21 +0000 |
| commit | 3c965dc3ac650b96097693d17cf1b96aec63b981 (patch) | |
| tree | e5b67676e4b1005efc15cd2a72790b4d3a101b50 | |
| parent | 92b78157022b0bd0777f84138f26ba879cef1028 (diff) | |
mb/siemens/mc_ehl2: Disable SATA
With latest hardware revision SATA interface is no longer used on this
mainboard. The mainboard is still in development and not yet released
and for this reason there may still be adjustments.
Change-Id: Icbf088ce4c907e207f6f5d11b8bf5556fe2c90d6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index acb928665e..4982384052 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -77,13 +77,7 @@ chip soc/intel/elkhartlake register "PcieRpLtrDisable[4]" = "true" register "PcieRpLtrDisable[6]" = "true" - # Storage (SATA/SDCARD/EMMC) related UPDs - register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "0" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" - + # Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "1" register "ScsEmmcDdr50Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" @@ -155,8 +149,6 @@ chip soc/intel/elkhartlake device pci 16.0 hidden end # Management Engine Interface 1 - device pci 17.0 on end # SATA - device pci 19.0 on end # I2C4 device pci 19.1 on end # I2C5 device pci 19.2 on end # UART2 |