diff options
| author | Matt DeVillier <matt.devillier@puri.sm> | 2022-01-25 19:52:44 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-28 17:55:05 +0000 |
| commit | 3b6d202ee5ff944f418258cfe327e4d1d806e618 (patch) | |
| tree | 6e7c60e0630b7573b2abc7429f6663e00ad0eac3 | |
| parent | eaac053d2391d65b8e23f624c4c08a83fdbaae0f (diff) | |
mb/purism/librem_skl: disable HECI PCI device
As all librem_skl devices ship with the ME disabled via HAP bit and ME
firmware "neutralized" via me_cleaner, the HECI1 PCI device should be
marked off/disabled to ensure that heci_reset() is not called at the end
of heci_init(), as this causes a 15s timeout delay when booting
(introduced in commit cb2fd20 [soc/intel/common: Add HECI Reset flow in
the CSE driver]).
Change-Id: Ib6bfcfd97e32bb9cf5be33535d77eea8227a8f9f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/purism/librem_skl/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index ef898b2a19..94b79f9bc9 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -160,7 +160,7 @@ chip soc/intel/skylake device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 14.3 off end # Camera - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection |