mb/hp/280_g2: Make use of the chipset devicetree

Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.

Change-Id: Ib6edae61fb904143c3b3994df812524a258fa9f3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

1 files changed, 22 insertions, 46 deletions

diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb
index 18a5a08183..d6c8bc03e5 100644
--- a/src/mainboard/hp/280_g2/devicetree.cb
+++ b/src/mainboard/hp/280_g2/devicetree.cb
@@ -10,12 +10,11 @@ chip soc/intel/skylake
 	device cpu_cluster 0 on end
 	device domain 0 on
 		subsystemid 0x103c 0x2b5e inherit
-		device pci 00.0 on  end		# Host bridge
-		device pci 01.0 on  end		# PCIe graphics
-		device pci 02.0 on  end		# iGPU
-		device pci 04.0 on  end		# CPU Thermal
-		device pci 08.0 on  end		# GMM
-		device pci 14.0 on		# xHCI
+		device ref peg0		on	end
+		device ref igpu		on	end
+		device ref sa_thermal	on	end
+		device ref gmm		on	end
+		device ref south_xhci	on
 			register "usb2_ports" = "{
 				[0]  = USB2_PORT_MID(OC0),
 				[1]  = USB2_PORT_MID(OC0),
@@ -45,26 +44,17 @@ chip soc/intel/skylake
 				[9] = USB3_PORT_DEFAULT(OC_SKIP),
 			}"
 		end
-		device pci 14.1 off end		# USB OTG
-		device pci 14.2 on  end		# PCH Thermal
-		device pci 15.0 off end		# I2C #0
-		device pci 15.1 off end		# I2C #1
-		device pci 15.2 off end		# I2C #2
-		device pci 15.3 off end		# I2C #3
-		device pci 16.0 on  end		# MEI #1
-		device pci 16.1 off end		# MEI #2
-		device pci 16.2 off end		# ME IDE-R
-		device pci 16.3 off end		# ME KT
-		device pci 16.4 off end		# MEI #3
-		device pci 17.0 on		# SATA
-			register "SataSalpSupport"	= "1"
-			register "SataPortsEnable"	= "{
+		device ref thermal	on	end
+		device ref heci1	on	end
+		device ref sata		on
+			register "SataSalpSupport" = "1"
+			register "SataPortsEnable" = "{
 				[0] = 1,
 				[1] = 1,
 				[2] = 1,
 				[3] = 1,
 			}"
-			register "SataPortsHotPlug"	= "{
+			register "SataPortsHotPlug" = "{
 				[0] = 1,
 				[1] = 1,
 				[2] = 1,
@@ -72,64 +62,50 @@ chip soc/intel/skylake
 			}"
 			# DevSlp not supported
 		end
-		device pci 19.0 on  end		# UART #2
-		device pci 1c.0 off end		# RP #1
-		device pci 1c.1 off end		# RP #2
-		device pci 1c.2 off end		# RP #3
-		device pci 1c.3 off end		# RP #4
-		device pci 1c.4 on		# RP #5: IT8893E PCI Bridge
+		device ref uart2	on	end
+		device ref pcie_rp5	on
 			register "PcieRpEnable[4]"			= "1"
 			register "PcieRpLtrEnable[4]"			= "1"
 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
 			register "PcieRpClkSrcNumber[4]"		= "11"
 		end
-		device pci 1c.5 on		# RP #6: PCIe x1 slot
+		device ref pcie_rp6	on
 			register "PcieRpEnable[5]"			= "1"
 			register "PcieRpHotPlug[5]"			= "1"
 			register "PcieRpLtrEnable[5]"			= "1"
 			register "PcieRpAdvancedErrorReporting[5]"	= "1"
 			register "PcieRpClkSrcNumber[5]"		= "6"
 		end
-		device pci 1c.6 on		# RP #7: RTL8111 GbE NIC
+		device ref pcie_rp7	on
 			register "PcieRpEnable[6]"			= "1"
 			register "PcieRpLtrEnable[6]"			= "1"
 			register "PcieRpAdvancedErrorReporting[6]"	= "1"
 			register "PcieRpClkSrcNumber[6]"		= "10"
 		end
-		device pci 1c.7 on		# RP #8: M.2 2230 slot
+		device ref pcie_rp8	on
 			register "PcieRpEnable[7]"			= "1"
 			register "PcieRpHotPlug[7]"			= "1"
 			register "PcieRpLtrEnable[7]"			= "1"
 			register "PcieRpAdvancedErrorReporting[7]"	= "1"
 			register "PcieRpClkSrcNumber[7]"		= "12"
 		end
-		device pci 1d.0 off end		# RP #9
-		device pci 1d.1 off end		# RP #10
-		device pci 1d.2 off end		# RP #11
-		device pci 1d.3 off end		# RP #12
-		device pci 1e.0 off end		# UART #0
-		device pci 1e.1 off end		# UART #1
-		device pci 1e.2 off end		# GSPI #0
-		device pci 1e.3 off end		# GSPI #1
-		device pci 1f.0 on		# LPC bridge
+		device ref lpc_espi	on
 			register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
 			# FIXME: Missing Super I/O HWM config
 			register "gen1_dec" = "0x000c0291"
 		end
-		device pci 1f.1 on  end		# P2SB
-		device pci 1f.2 on		# PMC
+		device ref pmc		on
 			register "PmConfigSlpS3MinAssert"	= "SLP_S3_MIN_ASSERT_50MS"
 			register "PmConfigSlpS4MinAssert"	= "SLP_S4_MIN_ASSERT_4S"
 			register "PmConfigSlpSusMinAssert"	= "SLP_SUS_MIN_ASSERT_4S"
 			register "PmConfigSlpAMinAssert"	= "SLP_A_MIN_ASSERT_2S"
 			register "PmConfigPwrCycDur"		= "RESET_POWER_CYCLE_4S"
 		end
-		device pci 1f.3 on  end		# Intel HDA
-		device pci 1f.4 on  end		# SMBus
-		device pci 1f.5 on  end		# SPI
-		device pci 1f.6 off end		# Intel GbE
-		device pci 1f.7 on		# Trace Hub
+		device ref hda		on	end
+		device ref smbus	on	end
+		device ref fast_spi	on	end
+		device ref tracehub	on
 			register "TraceHubMemReg0Size" = "2"
 			register "TraceHubMemReg1Size" = "2"
 		end