diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-04-19 18:38:03 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-04-22 05:37:18 +0000 |
| commit | 3879334ca0d73c84a03416a73fcf52c95f39ba6b (patch) | |
| tree | b9f518f58a6ddecde636a10b3d103d7b57d03a68 | |
| parent | 534cc06d6047fff5a756e956695b9cbaf2f59261 (diff) | |
mb/google/rex: Enable asynchronous End-Of-Post
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about
100ms on google/rex.
TEST=Tests on google/rex with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
| -rw-r--r-- | src/mainboard/google/rex/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 62ece95918..528a2dc2c4 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -27,6 +27,7 @@ config BOARD_GOOGLE_REX_COMMON select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_CSE_SEND_EOP_ASYNC config BOARD_GOOGLE_BASEBOARD_REX def_bool n diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index c34f255be7..7762d5f0ec 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -89,7 +89,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_IOC - select SOC_INTEL_CSE_SEND_EOP_LATE + select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION |