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authorShuo Liu <shuo.liu@intel.com>2024-04-02 22:10:20 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-04-04 09:01:42 +0000
commit37a2fb535356efd016ccdb24f1824690c01f7b2a (patch)
tree30cc35f4fb25c8397cd75bb610c1f9f7e69e8e65
parent698fa27e82e6f83467bb5bcc777741b10e674abb (diff)
soc/intel/xeon_sp: Use default soc_get_ioapic_info
intel/common/block/acpi provides default soc_get_ioapic_info for single IOAPIC model. Use the default soc_get_ioapic_info when XEON_SP_HAVE_IIO_IOAPIC is not set. This model fits for SPR and later. TEST=Build and boot on intel/archercity CRB Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/soc/intel/xeon_sp/acpi.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c
index de63ced7b6..9ee8d6a59b 100644
--- a/src/soc/intel/xeon_sp/acpi.c
+++ b/src/soc/intel/xeon_sp/acpi.c
@@ -90,6 +90,7 @@ const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
return map;
}
+#if CONFIG(XEON_SP_HAVE_IIO_IOAPIC)
static uintptr_t xeonsp_ioapic_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1];
size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
@@ -126,6 +127,7 @@ size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
return index;
}
+#endif
void iio_domain_set_acpi_name(struct device *dev, const char *prefix)
{